FS7140, FS7145

http://onsemi.com

11

Programming Information

All register bits are cleared to zero on power−up. All register bits may be read back as written.

Table 7. FS7140 REGISTER MAP

Address

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Byte 7

Reserved

(Bit 63)

Must be set

to “0”

Reserved

(Bit 62)

Must be set

to “0”

Reserved

(Bit 61)

Must be set

to “0”

Reserved

(Bit 60)

Must be set

to “0”

Reserved

(Bit 59)

Must be set

to “0”

Reserved

(Bit 58)

Must be set

to “0”

Reserved

(Bit 57)

Must be set

to “0”

Reserved

(Bit 56)

Must be set

to “0”

Byte 6

Reserved

(Bit 55)

Must be set

to “0”

Reserved

(Bit 54)

Must be set

to “0”

SHUT2

(Bit 53)

0 = Normal

1 = Powered

down

Reserved

(Bit 52)

Must be set

to “0”

Reserved

(Bit 51)

Must be set

to “0”

Reserved

(Bit 50)

Must be set

to “0”

Reserved

(Bit 49)

Must be set

to “0”

Reserved

(Bit 48)

Must be set

to “0”

Byte 5

Reserved

(Bit 47)

Must be set

to “0”

LC

(Bit 46)

Loop filter

cap select

LR[1]

(Bit 45)

LR[0]

(Bit 44)

Reserved

(Bit 43)

Must be set

to “0”

Reserved

(Bit 42)

Must be set

to “0”

CP[1]

(Bit 41)

CP[0]

(Bit 40)

Loop filter resistor select

Charge pump current select

Byte 4

CMOS

(Bit 39)

0 = PECL

1 = CMOS

FBKDSRC

(Bit 38)

0 = VCO

output

1 = Post

divider output

FBKDIV[13]

(Bit 37)

8192

FBKDIV[12]

(Bit 36)

4096

FBKDIV[11]

(Bit 35)

2048

FBKDIV[10]

(Bit 34)

1024

FBKDIV[9]

(Bit 33)

512

FBKDIV[8]

(Bit 32)

256

See the Feedback Divider section for disallowed FBKDIV values

Byte 3

FBKDIV[7]

(Bit 31)

128

FBKDIV[6]

(Bit 30)

64

FBKDIV[5]

(Bit 29)

32

FBKDIV[4]

(Bit 28)

16

FBKDIV[3]

(Bit 27)

8

FBKDIV[2]

(Bit 26)

4

FBKDIV[1]

(Bit 25)

2

FBKDIV[0]

(Bit 24)

1

See the Feedback Divider section for disallowed FBKDIV values

Byte 2

POST2[3]

(Bit 23)

POST2[2]

(Bit 22)

POST2[1]

(Bit 21)

POST2[0]

(Bit 20)

POST1[3]

(Bit 19)

POST1[2]

(Bit 18)

POST1[1]

(Bit 17)

POST1[0]

(Bit 16)

Modulus = N + 1 (N = 0 to 11); See Table 12

Modulus = N + 1 (N = 0 to 11); See Table 12

Byte 1

POST3[1]

(Bit 15)

POST3[0]

(Bit 14)

SHUT1

(Bit 13)

0 = Normal

1 = Powered

down

REFDSRC

(Bit 12)

0 = Crystal

oscillator

1 = REF pin

REFDIV[11]

(Bit 11)

2048

REFDIV[10]

(Bit 10)

1024

REFDIV[9]

(Bit 9)

512

REFDIV[8]

(Bit 8)

256

Modulus = 1, 2, 4 or 8;

See Table 12

Byte 0

REFDIV[7]

(Bit 7)

128

REFDIV[6]

(Bit 6)

64

REFDIV[5]

(Bit 5)

32

REFDIV[4]

(Bit 4)

16

REFDIV[3]

(Bit 3)

8

REFDIV[2]

(Bit 2)

4

REFDIV[1]

(Bit 1)

2

REFDIV[0]

(Bit 0)

1