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0W633-001-XTP Datasheet(PDF) 14 Page - ON Semiconductor

Part No. 0W633-001-XTP
Description  High-Performance Programmable Audio Processing System
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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0W633-001-XTP Datasheet(HTML) 14 Page - ON Semiconductor

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BELASIGNA 250
http://onsemi.com
14
Figure 3. RCore DSP Architecture
XRAM
X_Bus
YRAM
Y_Bus
Y_AGU
Data registers
Address and Control registers
P_Bus
R4
R5
R6
R7
PCFG6
PCFG5
PCFG4
CTRL
Multiplier
XY
PH
PL
ALU
Barrel
Shifter
DCU
AE
AH
AL
Limiter
EXP
ST
Internal Routing
Internal Routing
PC
Immediate
PRAM
PCU
LC0
LC1
REP
D_SYS_CTRL
D_INT_EBL
D_INT_STATUS
EXT3
D_AUX_REG4
D_AUX_REG0
X_AGU
R0
R1
R2
R3
PCFG2
PCFG1
PCFG0
The RCore is a single−cycle pipelined multiply−
accumulate (MAC) architecture that feeds into a 40−bit
accumulator
complete
with
barrel
shifter
for
fast
normalization and de−normalization operations. Program
execution is controlled by a sequencer that employs a
three−stage pipeline (FETCH, DECODE, EXECUTE).
Furthermore, the RCore incorporates pointer configuration
registers for low cycle−count address generation when
accessing the three memories: program memory (PRAM),
X data memory (XRAM) and Y data memory (YRAM).
Instruction Set
The RCore instruction set can be divided into the
following three classes:
1. Arithmetic and Logic Instructions
The RCore uses two’s−complement fractional as a native
data format. Thus, the range of valid numbers is [−1; 1),
which is represented by 0x8000 to 0x7FFF. Other formats
can be utilized by applying appropriate shifts to the data.
The multiplier takes 16−bit values and performs a
multiplication every time an operand is loaded into either the
X or Y registers. A number of instructions that allow loading
of X and Y simultaneously and addition of the new product
to the previous product (a MAC operation) are available.
Single−cycle MAC with data pointer update and fetch is
supported.
The arithmetic logic unit (ALU) receives its input from
either the accumulator (AE|AH|AL) or the product register
(PH|PL). Although the RCore is a 16−bit system, 32−bit
additions
or
subtractions
are
also
supported.
Bit
manipulation is also available on the accumulator, as are
operations to perform arithmetic or logic shifting, toggling
of specific bits, limiting, and other functions.
2. Data Movement Instructions
Data movement instructions transfer data between RAM,
control registers and the RCore’s internal registers
(accumulator, PH, PL, etc.).
Two address generators are available to simultaneously
generate two addresses in a single cycle. The address
pointers R0..2 and R4..6 can be configured to support
increment, decrement, add−by−offset, and two types of
modulo−N circular buffer operations. Single−cycle access
to low−X memory or low−Y memory as well as two−cycle
instructions for immediate access to any address, are also
available.
3. Program Flow Control Instructions
The RCore supports repeating of both single−word
instructions and larger segments of code using dedicated
repeat instructions or hardware loop counters. Furthermore,
instructions to manipulate the program counter (PC) register
such as calls to subroutines, conditional branches and
unconditional branches are also provided.
The full instruction set may be seen in Table 7.


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