ASM3P2508A

http://onsemi.com

6

An example of a Byte Write via I2C to partially ‘power down’ the device:

ASM3P2508A can be partially ‘powered down’ using bit 1 of Byte 0. The organization of the register bits for Byte ‘0’ is

given with default values below:

Bit

7

6

5

4

3

2

1

0

Resv

Resv

Resv

Resv

Resv

Resv

PLL2 Enable

PLL1 Enable

0

1

0

1

0

1

1

1

The function of partial power down of the device is of

interest to us − that is bit 1 of Byte 0. In the default mode this

bit is logic ‘1’. As such, the Byte 0 default value is 57 (H).

To put ASM3P2508A in ‘power down’ mode, the bit 1 of

Byte 0 is to be changed to logic ‘0’. Hence writing a 55 (H)

via I2C into Byte 0 would put the device in partial ‘power

down’ mode where the PLL block generating 72 MHz /

48 MHz would be powered down while I2C block, crystal

oscillator, and the PLL block generating 120 MHz would

still be active. The organization of the register bits is as

below:

Bit

7

6

5

4

3

2

1

0

Resv

Resv

Resv

Resv

Resv

Resv

PLL2 Enable

PLL1 Enable

0

1

0

1

0

1

0

1

Byte 0

Byte 1

FOUT1CLK (MHz)

FOUT2CLK (MHz)

Power up default

6F (H)

3F (H)

120

72

48_MHz Mode

6F (H)

BF (H)

120

48

Power down PLL with 72 MHz

6D (H)

3F (H)

120

−

Power down PLL with 48 MHz

6D (H)

BF (H)

120

−

Figure Showing a Complete Data Transfer: