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NL17SHT126 Datasheet(PDF) 1 Page - ON Semiconductor |
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NL17SHT126 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 5 page © Semiconductor Components Industries, LLC, 2011 August, 2011 − Rev. 0 1 Publication Order Number: NL17SHT126/D NL17SHT126 Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs The NL17SHT126 is a single gate noninverting 3−state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The NL17SHT126 requires the 3−state control input (OE) to be set Low to place the output into the high impedance state. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V CMOS Logic while operating at the high−voltage power supply. The NL17SHT126 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the NL17SHT126 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. Features • High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V • Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C • TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V • CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load • Power Down Protection Provided on Inputs and Outputs • Balanced Propagation Delays • Pin and Function Compatible with Other Standard Logic Families • These are Pb−Free Devices Figure 1. Pinout (Top View) IN A OUT Y VCC OE IN A OUT Y GND OE Figure 2. Logic Symbol 1 2 3 4 5 PIN ASSIGNMENT 1 2 3OE IN A GND 4 5VCC OUT Y See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION FUNCTION TABLE L H X A Input Y Output L H Z OE Input H H L http://onsemi.com MARKING DIAGRAM SOT−953 CASE 527AE R = Specific Device Code M = Month Code RM 1 |
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