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INA220B-Q1 Datasheet(PDF) 11 Page - Texas Instruments |
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INA220B-Q1 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 40 page  INA220B-Q1 www.ti.com SLOS785A – JUNE 2012 – REVISED JUNE 2012 Serial Interface When reading from the INA220B-Q1 device, the last value stored in the register pointer by a write The INA220B-Q1 device operates only as a slave operation determines which register is read during a device on the 2-wire bus and SMBus. Connections to read operation. To change the register pointer for a the bus are made through the open-drain I/O lines read operation, a new value must be written to the SDA and SCL. The SDA and SCL pins feature register pointer. This write is accomplished by issuing integrated spike suppression filters and Schmitt a slave address byte with the R/W bit LOW, followed triggers to minimize the effects of input spikes and by the register pointer byte. No additional data are bus noise. The INA220B-Q1 device supports the required. The master then generates a START transmission protocol for fast (1 kHz to 400 kHz) and condition and sends the slave address byte with the high-speed (HS) (1 kHz to 3.4 MHz) modes. All data R/W bit HIGH to initiate the read command. The next bytes are transmitted most significant byte first. byte is transmitted by the slave and is the most significant byte of the register indicated by the WRITING TO AND READING FROM THE register pointer. This byte is followed by an INA220B-Q1 DEVICE Acknowledge from the master; then the slave transmits the least significant byte. The master Accessing a particular register on the INA220B-Q1 acknowledges receipt of the data byte. The master device is accomplished by writing the appropriate may terminate data transfer by generating a Not- value to the register pointer. Refer to Table 3 for a Acknowledge after receiving any data byte, or complete list of registers and corresponding generating a START or STOP condition. If repeated addresses. The value for the register pointer as reads from the same register are desired, it is not shown in Figure 17 is the first byte transferred after necessary to continually send the register pointer the slave address byte with the R/W bit LOW. Every bytes; the INA220B-Q1 device retains the register write operation to the INA220B-Q1 device requires a pointer value until it is changed by the next write value for the register pointer. operation. Writing to a register begins with the first byte Figure 14 and Figure 15 show read and write transmitted by the master. This byte is the slave operation timing diagrams, respectively. Note that address, with the R/W bit LOW. The INA220B-Q1 register bytes are sent most significant byte first, device then acknowledges receipt of a valid address. followed by the least significant byte. Figure 16 The next byte transmitted by the master is the shows the timing diagram for the SMBus ALERT address of the register to which data will be written. response operation. Figure 17 illustrates a typical This register address value updates the register register pointer configuration. pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The INA220B-Q1 device acknowledges receipt of each data byte. The master may terminate data transfer by generating a START or STOP condition. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): INA220B-Q1 |
Similar Part No. - INA220B-Q1_15 |
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Similar Description - INA220B-Q1_15 |
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