LM77

www.ti.com

SNIS103F – JUNE 1999 – REVISED MARCH 2013

Logic Electrical Characteristics Digital DC Characteristics (continued)

otherwise noted.

Units

Parameter

Test Conditions

(Limit)

Low Level Output Voltage

0.4

V (max)

T_CRIT_A Output Saturation Voltage

(3)

0.8

V (max)

T_CRIT_A Delay

1

Conversions

(max)

Output Fall Time

250

ns (max)

(3)

For best accuracy, minimize output loading. Higher sink currents can affect sensor accuracy with internal heating. This can cause an

error of 0.64°C at full rated sink current and saturation voltage based on junction-to-ambient thermal resistance.

Logic Electrical Characteristics Serial Bus Digital Switching Characteristics

±10% for LM77CIM-3 and LM77CIMM-3, CL (load capacitance) on output lines = 80 pF unless otherwise specified. Boldface

Units

Parameter

Test Conditions

(Limit)

SCL (Clock) Period

2.5

μs(min)

Data in Set-Up Time to SCL High

100

ns(min)

Data Out Stable after SCL Low

0

ns(min)

SDA Low Set-Up Time to SCL Low (Start Condition)

100

ns(min)

SDA High Hold Time after SCL High (Stop Condition)

100

ns(min)

(1)

(2)

Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).

(3)

Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when

the SCL and SDA edge rates are similar.

Figure 4.

Copyright © 1999–2013, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Links: LM77