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ATMEGA32-16MC Datasheet(PDF) 81 Page - ATMEL Corporation |
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ATMEGA32-16MC Datasheet(HTML) 81 Page - ATMEL Corporation |
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81 / 317 page  81 ATmega32(L) 2503F–AVR–12/03 Timer/Counter Interrupt Flag Register – TIFR • Bit 1 – OCF0: Output Compare Flag 0 The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Com- pare Match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed. • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (T im er/C o un ter 0 O ve rflo w In ter rup t En ab le ), a n d TO V 0 a re s et (o ne ), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00. Bit 765 43 21 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 00 00 0 |
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