LM75B, LM75C

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SNIS153D – JULY 2009 – REVISED OCTOBER 2015

6.7 I

PARAMETER

TEST CONDITIONS

UNIT

SCL (Clock) Period, See Figure 1

–55°C

2.5

µs

Data in Set-Up Time to SCL High, See Figure 1

–55°C

100

ns

Data Out Stable after SCL Low, See Figure 1

–55°C

0

ns

SDA Low Set-Up Time to SCL Low (Start Condition),

ns

–55°C

100

See Figure 1

SDA High Hold Time after SCL High (Stop Condition),

ns

–55°C

100

See Figure 1

LM75B

–55°C

75

325

ms

Not

LM75C

Applicable

(1)

Limits are specified to AOQL (Average Outgoing Quality Level).

(2)

Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when

the SCL and SDA edge rates are similar.

(3)

(4)

communication (SDA set High).

Figure 1. Timing Diagram

Figure 2. Temperature-to-Digital Transfer Function (Non-Linear Scale for Clarity)

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