9-18

DG200, DG201

Test Circuits

FIGURE 5.

FIGURE 6.

FIGURE 7.

0V

3V

LOGIC

INPUT

ANALOG

INPUT 10V

10pF

1k

Ω

NOTE: All channels are turned off by high “1” logic inputs and

all channels are turned on by low “0” inputs; however 0.8V to

2.4V describes the minimum range for switching properly.

Peak input current required for transition is typically -120

0V

3V

LOGIC

INPUT

ANALOG

INPUT 10V

10,000pF

100

Ω

LOGIC

INPUT *

51

Ω

* Pull Down Resistor must be

Typical Applications

The DG200 and DG201 have an internal voltage divider set-

ting the TTL threshold on the input control lines for V+ equal

to +15V. The schematic shown in Figure 8 with nominal

As the TTL input signal goes from +0.8V to +2.4V, Q1 and

Q2 switch states to turn the switch ON and OFF.

FIGURE 8.

V+ (+15V)

Q1

31k

Ω

6k

Ω

Q2

GATE

PROTECTION

RESISTOR

INPUT

If the power supply voltage is less than +15V, then a resistor

various supply voltages, to maintain TTL compatibility. If

CMOS logic levels on a +5V supply are being used, the

threshold shifts are less critical, but a separate column of

suitable values is given in the table. For logic swings of -5V

to + 5V, no resistor is needed.

In general, the “low” logic level should be <0.8V to prevent

Q1 and Q2 from both being ON together (this will cause

incorrect switch function).

TABLE 1.

V+ SUPPLY (V)

TTL RESISTOR

(k

Ω)

CMOS RESISTOR

(k

Ω)

+15

-

-

+12

100

-

+10

51

-

+9

(34)

34

+8

(27)

27

+7

18

18