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SM5906AF Datasheet(PDF) 21 Page - Nippon Precision Circuits Inc

Part # SM5906AF
Description  Shock-proof Memory Controller for Video CD Players
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Manufacturer  NPC [Nippon Precision Circuits Inc]
Direct Link  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5906AF Datasheet(HTML) 21 Page - Nippon Precision Circuits Inc

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NIPPON PRECISION CIRCUITS-21
SM5906AF
Shock-proof mode is the mode that realizes shock-
proof operation using external DRAM. Shock-proof
mode is invoked by setting MSON=H in microcon-
troller command 80H.
This mode comprises the following 3 sequences.
Shock-proof operation overview
– Write sequence
1. Input data from a signal processor IC is read in.
2. Data read in is written to external DRAM in the
sequence left-channel, (C2PO), and right-channel.
(C2PO) is omitted in CDDA mode.
– Read sequence
1. Data written to external DRAM is read out at fs
rate (rate 2fs in SVC mode).
2. Data is output in sync with the 24-bit bit clock
(ZSCK).
– Compare-connect sequence
1. Encoding immediately stops when either external
buffer RAM overflows or when a CD read error
occurs due to shock vibrations.
2. Then, using microcontroller command 80H, the
compare-connect start command is executed
and compare-connect sequence starts.
3. Compares data re-read from the CD with the pro-
cessed final valid data stored in RAM (confirms
its correctness).
4. As soon as the comparison detects conforming
data, compare-connect sequence stops and
encode sequence re-starts, connecting the data
directly behind previous valid data.
RAM addresses
The SM5906AF uses 4M or 16M DRAMs as exter-
nal buffers.
Three kinds of addresses are used for external
RAM control.
WA (write address)
RA (read address)
VWA (valid write address)
Among these, VWA is the write address for con-
forming data whose validity has been confirmed.
Determination of the correctness of data read from
the CD is delayed relative to the write processing,
so VWA is always delayed relative to WA.
The region available for valid data is the area
between VWA-RA.
Fig 1. RAM addresses
RA
WA
VWA
Valid data
area


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