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NCP6914AFCAT1G Datasheet(PDF) 7 Page - ON Semiconductor |
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NCP6914AFCAT1G Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 36 page NCP6914 http://onsemi.com 7 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified. AVIN = PVIN1 = VIN12 = VIN3 = VIN4 = 3.6 V (unless otherwise noted). DCDC Output Voltage = 1.2 V, LDO1&2 = 1.8 V, LDO3&4 = 2.8 V, Typical values are referenced to TJ = + 25°C and default configuration (Note 10) Symbol Unit Max Typ Min Conditions Parameter HWEN VIH Positive Going Input High Voltage Threshold 1.1 − − V VIL Negative Going Input Low Voltage Threshold − − 0.4 V tHWEN Hardware Enable Filter HWEN rising and falling (Note 11) 4 − 9 ms IHWEN Hardware Enable Pull−Down (input bias current) − 0.1 1 mA PG VPGL Power Good Low Threshold VOUT falls down to cross the threshold (percentage of FB voltage) 86 90 of VNOM 94 % VPGHYS Power Good Hysteresis VOUT rises up to cross the threshold (percentage of Power Good Low Threshold (VPGL) voltage) 0 3 5 % tRT Power Good Reaction Time for DCDC Falling (Note 11) Rising (Note 11) − 4 5 − − 9 ms VPGL Power Good Low Output Voltage IPG = 5 mA − − 0.2 V PGLK Power Good Leakage Current 3.6 V at PG pin when power good valid − − 100 nA VPGH Power Good High Output Voltage Open drain − − 5.5 V INTB VINTBL INTB Low Output Voltage IINT = 5 mA 0 − 0.2 V VINTBH INTB High Output Voltage Open drain − − 5.5 V INTBLK INTB Leakage Current 3.6 V at INTB pin when INTB valid − − 100 nA I2C VI2CINT High Level at SCL/SDA Line − − 5.0 V VI2CIL SCL, SDA Low Input Voltage SCL, SDA pin (Notes 9 and 11) − − 0.5 V VI2CIH SCL, SDA High Input Voltage SCL, SDA pin (Notes 9 and 11) 0.8 x VI2CINT − − V VI2COL SCL, SDA Low Output Voltage ISINK = 3 mA (Note 11) − − 0.4 V FSCL I2C Clock Frequency − − 3.4 MHz TOTAL DEVICE VUVLO Under Voltage Lockout VIN falling − − 2.3 V VUVLOH Under Voltage Lockout Hysteresis VIN rising 60 − 200 mV TSD Thermal Shut Down Protection 150 °C TWARNING Warning Rising Edge 135 °C TSDH Thermal Shut Down Hysteresis 35 °C 9. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to the VDD voltage to which the pull−up resistors RP are connected. 10. Refer to the Application Information section of this data sheet for more details. 11. Guaranteed by design and characterized. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. |
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