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SM5905AF Datasheet(PDF) 8 Page - Nippon Precision Circuits Inc

Part # SM5905AF
Description  compression and non compression type shock-proof memory controller
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Manufacturer  NPC [Nippon Precision Circuits Inc]
Direct Link  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5905AF Datasheet(HTML) 8 Page - Nippon Precision Circuits Inc

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NIPPON PRECISION CIRCUITS-8
SM5905AF
Parameter
Symbol
Condition
Rating
Unit
Min
Typ
Max
ZSCK pulsewidth
tSCOW
15 pF load
1/96fs
ZSCK pulse cycle
tSCOY
15 pF load
1/48fs
ZSRDATA and ZLRCK output delay time
tDHL
15 pF load
0
60
ns
tDLH
15 pF load
0
60
ns
DRAM access timing (NRAS, NCAS2, NWE, A0 to A9, D0 to D3)
Parameter
Symbol
Condition
Rating
Unit
Min
Typ
Max
NRAS pulsewidth
tRASL
15 pF load
5
tCY(note)
tRASH
15 pF load
3
tCY
NRAS falling edge to NCAS2 falling edge
tRCD
15 pF load
2
tCY
NCAS2 pulsewidth
tCASH
15 pF load
5
tCY
tCASL
15 pF load
3
tCY
NRAS
Setup time
tRADS
15 pF load
1
tCY
falling edge to address
Hold time
tRADH
15 pF load
1
tCY
NCAS2
Setup time
tCADS
15 pF load
1
tCY
falling edge to address
Hold time
tCADH
15 pF load
5
tCY
NCAS2
Setup time
tCWDS
15 pF load
3
tCY
falling edge to data write
Hold time
tCWDH
15 pF load
3
tCY
NCAS2
Input setup
tCRDS
40
ns
rising edge to data read
Input hold
tCRDH
0ns
NWE pulsewidth
tWEL
15 pF load
6
tCY
NWE falling edge to NCAS2 falling edge
tWCS
15 pF load
3
tCY
Refresh cycle
Non compression
2.8
ms
(fs = 44.1 kHz playback)
tREF
4M
6-bit compression
7.3
ms
Memory system ON
DRAM 8-bit compression
5.5
ms
Decode sequence operation(READ=H)
× 1 or × 2 4-bit compression
10.9
ms
Note.
tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz
ZSCK
ZSRDATA
0.5VDD
DLH
ZLRCK
0.5VDD
DHL
ttDLH
SCOW
t
tSCOW
t
SCOY
t
Serial output (ZSRDATA, ZLRCK, ZSCK pins)


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