3

SP8853A/B

2V

2V

2V

LAST DATA BIT

FIRST DATA BIT

DATA

CLOCK

ENABLE

FREQUENCY (MHz)

400

350

300

250

200

150

100

50

0

0

25

500

650

750

1000

1300

1500

150

80

GUARANTEED

OPERATING

WINDOW

GUARANTEED

OPERATING

WINDOW

TYPICAL OVERLOAD

TYPICAL SENSITIVITY

Fig. 4 Typical input characteristics and input drive requirements for SP8853 A and B

Fig. 5 Data and clock timing requirements