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SP5748 Datasheet(PDF) 5 Page - Mitel Networks Corporation |
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SP5748 Datasheet(HTML) 5 Page - Mitel Networks Corporation |
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5 / 15 page  5 SP5748 Advance Information The RF signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier is fed to the 17 bit fully programmable counter, which is of MN+A architecture. The M counter is 13 bit and the A counter 4 The output of the programmable counter is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into1 of 16 ratios as descried in Figure 7. The output of the phase detector feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. The charge pump current setting is described in Figure 5, A buffered crystal reference frequency suitable for driving further synthesisers is available from pin 9. If not required this output can be disabled by connecting to Vcc The programmable divider output divided by 2, Fpd/2 and comparison frequency, Fcomp can be switched to ports P0 and P1 respectively by switching the device into test mode. The test modes are described in Figure 8. ABSOLUTE MAXIMUM RATINGS All voltages are referred to V EE at 0V Characteristic Pin Min Typ Max Units Conditions Supply voltage, Vcc 10 -0.3 7 V RF input voltage 11,12 2.5 Vp-p Differential across pins 11 and 12 RF input DC offset 11,12 -0.3 Vcc+0.3 V Port voltage 7,8 -0.3 Vcc+0.3 V Charge pump DC offset 1 -0.3 Vcc+0.3 V Varactor drive DC offset 14 -0.3 Vcc+0.3 V Crystal DC offset 2,3 -0.3 Vcc+0.3 V Buffered ref output 9 -0.3 Vcc+0.3 V Data, clock & enable 5,6,4 -0.3 Vcc+0.3 V DC offset Storage temperature -55 +125 °C Junction temperature +150 °C MP14 thermal resistance, chip to ambient 81 °C/W chip to case 27 °C/W Power consumption at TBC mW All ports off Vcc=5.5V ESD protection 2 kV Mil-std 883B latest revision method 3015 cat.1. Functional description The SP5748 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with excellent phase noise performance, even with high comparison frequencies. The package and pin allocation is shown in Figure 1 and the block diagram in Figure 2. The SP5748 is controlled by a standard 3-wire bus comprising data, clock and enable inputs. The programming word contains 26 bits, two of which are used for port selection, 17 to set the programmable divider ratio, four bits to select the reference division ratio, bits RD & R0-R2, see Figure 7, two bits to set charge pump current, bit C0 and C1, see Figure 5, and the remaining bit to access test modes, bit T0, see Figure 8. The programming format is shown in Figure 4. The clock input is disabled by an enable low signal, data is therefore only loaded into the internal shift registers during an enable high and is clocked into the controlling buffers by an enable high to low transition. This load is also synchronised with the programmable divider so giving smooth fine tuning. |
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Similar Description - SP5748 |
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