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TMP75-Q1 Datasheet(PDF) 11 Page - Texas Instruments |
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TMP75-Q1 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 31 page TMP175-Q1, TMP75-Q1 www.ti.com SBOS759 – NOVEMBER 2015 The TMP75-Q1 features three address pins, allowing up to eight devices to be connected per bus. Pin logic levels are described in Table 3. The address pins of the TMP175-Q1 and TMP75-Q1 are read after reset, at start of communication, or in response to a two-wire address acquire request. After the state of the pins are read, the address is latched to minimize power dissipation associated with detection. Table 3. Address Pins and Slave Addresses for the TMP75-Q1 A2 A1 A0 SLAVE ADDRESS 0 0 0 1001000 0 0 1 1001001 0 1 0 1001010 0 1 1 1001011 1 0 0 1001100 1 0 1 1001101 1 1 0 1001110 1 1 1 1001111 7.3.2.3 Writing and Reading to the TMP175-Q1 and TMP75-Q1 Accessing a particular register on the TMP175-Q1 and TMP75-Q1 devices is accomplished by writing the appropriate value to the Pointer register. The value for the Pointer register is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the TMP175-Q1 and TMP75-Q1 requires a value for the Pointer register (see Figure 7). When reading from the TMP175-Q1 and TMP75-Q1 devices, the last value stored in the Pointer register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer register. This action is accomplished by issuing a slave address byte with the R/W bit low, followed by the Pointer register byte. No additional data are required. The master can then generate a START condition and send the slave address byte with the R/W bit high to initiate the read command; see Figure 9 for details of this sequence. If repeated reads from the same register are desired, the Pointer register bytes do not have to be continually sent because the TMP175-Q1 and TMP75-Q1 remember the Pointer register value until it is changed by the next write operation. Register bytes are sent MSB first, followed by the LSB. 7.3.2.4 Slave Mode Operations The TMP175-Q1 and TMP75-Q1 can operate as a slave receiver or slave transmitter. 7.3.2.4.1 Slave Receiver Mode The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP175-Q1 or TMP75- Q1 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer register. The TMP175-Q1 or TMP75-Q1 then acknowledges reception of the Pointer register byte. The next byte or bytes are written to the register addressed by the Pointer register. The TMP175-Q1 and TMP75-Q1 acknowledge reception of each data byte. The master can terminate data transfer by generating a START or STOP condition. 7.3.2.4.2 Slave Transmitter Mode The first byte is transmitted by the master and is the slave address, with the R/W bit high. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the Pointer register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master can terminate data transfer by generating a Not-Acknowledge bit on reception of any data byte, or by generating a START or STOP condition. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TMP175-Q1 TMP75-Q1 |
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