SA828

6

pdy

Counter reset

When the CR bit is active (i.e., Iow) the internal power

frequency phase counter is set to 0 degrees for the red

phase. It will remain at 0 degrees until the CR bit is released

(i.e., high).

Control Register Function

This 24-bit register contains the parameters that would

normally be modified during PWM cycles in order to control

the operation of the motor.

The parameters set in the control register are as follows:

Power frequency (speed)

Allows the power frequency of the PWM outputs to be

adjusted within the range specified in the initialisation register

Forward/reverse

Allows the direction of rotation of the AC motor to be

changed by changing the phase sequence of the PWM

outputs.

Power frequency amplitude

By altering the widths of the PWM output pulses while

maintaining their relative widths, the amplitude of the power

waveform is effectively altered whilst maintaining the same

power frequency.

Overmodulation

Allows the output waveform amplitude to be doubled so

that a quasi-squarewave is produced.

A combination of

overmodulation and a lower power frequency can be used to

achieve rapid braking in AC motors.

Output inhibit

Allows the outputs to be set to the low state while the PWM

generation continues internally. Useful for temporarily

inhibiting the outputs without having to to change other

register contents.

The power frequency range is a function of the carrier

waveform frequency (

determined by the 3-bit FRS word. The value of

m is determined

as shown in Table 5.

FRS word

Value of m

000

1

001

2

010

4

011

8

100

16

101

32

Table 5 Values of carrier frequency multiplicaion factor m

110

64

The power frequency range,

where

(as set by FRS).

384

x

m

X

X

DON’T

CARE

PULSE

DELAY

SELECT WORD

Fig. 7 Temporary register R2

PDY word

Value of pdy

000000

64

...etc...

...etc...

111110

2

Table 6 Values of pdy

111111

1

The pulse delay time,

where

frequency.

Fig 8 shows the eftect of the pulse delay circuit.

It should be noted that as the pulse delay circuit follows the

pulse deletion circuit (see Fig. 2), the minimum pulse width

seen at the PWM outputs will be shorter than the pulse deletion

time set in the initialisation register. The actual shortest pulse

generated is given by

Pulse delay time

The pulse delay time affects all six PWM outputs by delaying

the rising edges of each of the outputs by an equal amount.

The pulse delay time is a function of the carrier waveform

frequency and

pdy, defined by the 6-bit pulse delay time select

word (PDY). The value of

pdy is selected as shown in Table 6.

Fig. 8 Effect of pulse delay on PWM pulse train

PWM SIGNAL

REQUIRED AT

INVERTER OUTPUT

OUTPUT SIGNAL TO

DRIVE TOP SWITCH

INVERTER ARM

OUTPUT SIGNAL TO

DRIVE BOTTOM SWITCH

INVERTER ARM

CR

COUNTER

RESET

PULSE DELETION

TIME

SELECT WORD

Fig. 9 Temporary register R0

Pulse deletion time

To eliminate short pulses the true PWM pulse train is passed

through a pulse deletion circuit. The pulse deletion circuit

compares pulse widths with the pulse deletion time set in the

initialisation register. lf a pulse (either positive or negative) is

greater than or equal in duration to the pulse deletion time, it is

passed through unaltered, otherwise the pulse is deleted.

The pulse deletion time,

frequency and

pdt, defined by the 7-bit pulse deletion time word

(PDT). The value of

pdt is selected as shown in Table 7.

PDT word

Value of pdt

0000000

128

...etc...

...etc...

1111110

2

Table 7 Values of pdt

1111111

1

The pulse deletion time,

where

Fig. 10 shows the effect of pulse deletion on a pure PWM

waveform.

pdt