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PDSP16330MC Datasheet(PDF) 5 Page - Mitel Networks Corporation |
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PDSP16330MC Datasheet(HTML) 5 Page - Mitel Networks Corporation |
5 / 10 page PDSP16330 MC 5 Characteristic † Input data setup to clock rising edge † Input data Hold after clock rising edge † CEX, CEY Setup to clock rising edge † CEX, CEY Hold aher clock rising edge † FORM, S1:0 Setup to clock rising edge † FORM, S1:0 Hold after clock rising edge † Clock rising edge to valid data * Clock period † Clock high time † Clock low time † Latency † OEM, OEP low to data high data valid † OEM, OEP low to data low data valid † OEM, OEP high to data high impedance † OEM, OEP low to data high impedance † Vcc current (TTL input levels) † Vcc current (CMOS input levels) SWITCHING CHARACTERISTICS Min. 15 2 30 0 15 7 5 100 25 25 24 Max. 40 24 30 30 30 30 110 70 PDSP16330 Value Units ns ns ns ns ns ns ns ns ns ns cycles ns ns ns ns mA mA Conditions 2 x LSTTL + 20pF 2 x LSTTL + 20pF 2 x LSTTL + 20pF 2 x LSTTL + 20pF 2 x LSTTL + 20pF V CC = Max Outputs unloaded Clock freq. = Max V CC = Max Outputs unloaded Clock freq. = Max Sub- group 9,10,11 ABSOLUTE MAXIMUM RATINGS Supply voltage, V cc -0.5V to + 7.0V Input voltage, V IN -0.5V to VCC + 0.5V Output voltage, V our -0.5V to VCC + 0.5V Clamp diode current per pin, I K (see Note 2) ±18mA Static discharge voltage (HMB), V STAT 500V Storage temperature. T stg -65 °C to + 150°C Ambient temperature with power applied T amb: Military -55 °C to + 125 °C Package power dissipation P TOT 1200mW Junction temperature 150 °C THERMAL CHARACTERISTICS Package Type θJC°C/W GC 12 NOTES 1. Exceeding these ratings may cause permanent damage. Functional operatlon under these conditions is not implied. 2. Maximum dissipation or 1 second should not be exceeded; only one output to be tested at any one time. 3. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability NOTES 1. LSTTL is equivalent to I OH = 20µA, IOL = -0.4mA 2. Current is defined as negative into the device 3. CMOS input levels are defined as: V IH = VDD - 0.5V, VIL = +0.5V 4. All parameters marked * are tested during production. Parameters marked † are guaranteed by design and characterisation. 5. All timings are dependent on silicon speed. This speed is tested by measuring clock period. This guarantees all other timings by characterisation and design. |
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