P3P76Z11D, P3P76Z11DH

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4

Parameter

Test Conditions

Min

Typ

Max

Unit

Input Frequency

FS = 0

15

30

MHz

FS = 1

30

75

ModOUT

FS = 0

15

30

FS = 1

30

75

Duty Cycle (Notes 1 and 2)

45

(49−51)

55

%

Rise Time (Notes 1 and 2)

Measured between 20% to 80%

P3P76Z11D

1.3

2.1

ns

P3P76Z11DH

1

1.7

Fall Time (Notes 1 and 2)

Measured between 80% to 20%

P3P76Z11D

1.3

2.1

ns

P3P76Z11DH

1

1.7

Cycle−to−Cycle Jitter

(Note 2)

Unloaded output with

SSEXTR = OPEN

FS = 0

15 MHz

±150

ps

30 MHz

±100

FS = 1

30 MHz

±150

75 MHz

±100

Input−Output propagation

Delay (Note 2)

SSEXTR = OPEN, No load on DLY_CTRL and ModOUT

1.1

ns

Load line

Change in Input−Output delay (with

capacitive load ≤ 15 pF), SSEXTR =

OPEN

on DLY_CTRL

−35

ps/pF

on ModOUT

35

PLL Lock Time (Note 2)

Stable power supply, valid clock presented on CLKIN pin, PD#

toggled from Low to High

1

ms

1. All parameters are specified with 15 pF loaded output.

2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

SWITCHING WAVEFORMS

OUTPUT

Figure 2. Duty Cycle Timing

OUTPUT

20%

80%

20%

80%

Figure 3. Output Rise/Fall Time