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MT90710AP Datasheet(PDF) 7 Page - Mitel Networks Corporation

Part No. MT90710AP
Description  High-Speed Isochronous Multiplexer
Download  12 Pages
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Manufacturer  MITEL [Mitel Networks Corporation]
Direct Link  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

MT90710AP Datasheet(HTML) 7 Page - Mitel Networks Corporation

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Preliminary Information
MT90710
5-9
Receive
The 4B/5B and NRZI encoded data from the receive
fiber interface is NRZI decoded and the frame
synchronization information is extracted. After 4B/5B
decoding the remaining data is frame aligned either
to the system frame pulse (when in Controller Mode)
or to the extracted frame pulse (when in Peripheral
Mode). After alignment, the received data package is
disassembled
into
the
clear
channel
ST-BUS
streams,
the
asynchronous
signals
and
the
overhead/status information. When ST6MUX mode
is disabled, received 15.808 Mb/s bandwidth is made
available on STo0-STo6A and the last 23 channels of
STo7. The asynchronous signals are presented on
DOUT8K0, DOUT8K1 and DOUT32K while the
received overhead information, as well as local
status information, is presented on ST07 in channels
0 to 7.
Control
An external, 40.96 MHz PLL provides the master
clock (C40i) for the MT90710. This PLL uses either
the system’s C4b clock (pin 57) for reference when
it’s in controller mode or the extracted clock from the
receive data interface when it’s in peripheral mode.
Switching between these two primary references is
automatic and under the control of the MODE0-2
pins. The selected reference is fed to the external
PLL from the C4REFo output pin. The MT90710 also
divides the 40.96 MHz master clock by ten and
supplies this secondary reference to the external
PLL on C4o for comparison to the primary reference.
The PLL creates a 40.96 MHz master clock from a
4.096 MHz reference by multiplying by 10 and
attenuates jitter present on the extracted reference.
The master clock is divided down to create internal
clocks, external ST-BUS clocks (when in peripheral
mode) and timeslot counters.
Control signals are also created for the transmitter
and receiver. The transmitter timeslot counter is
synchronized to the backplane frame pulse while the
receiver timeslot counter is sync to the extracted
synchronization pulse.
Frame Buffer
To re-align the received data from the fiber interface
to the system, or node, a frame reference buffer is
C4o
(Pin 13)
ST-BUS input data latched here
122 ns
48.8ns
WR ADDR
RD ADDR
WR ADDR
RD ADDR
RD
WR
FBDATA
FBADDR
FBWE
FBOE
C20o
(Pin 6)
170.8ns
Bit Cell
Figure 4 - Frame Buffer Memory Typical Timing


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