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MT8982-1 Datasheet(PDF) 2 Page - Mitel Networks Corporation |
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MT8982-1 Datasheet(HTML) 2 Page - Mitel Networks Corporation |
2 / 19 page MT8982 ISO-CMOS 2-32 Figure 2 - Pin Connections Pin Description Pin # Name Description 16 20 1-2 1-2 STi0- STi1 Serial TDM Input 0 and 1 (Inputs). 2048 kbit/s input data streams containing 32 8-bit channels synchronized to F0i. 3-4 4-5 STo0- STo1 Serial TDM Output 0 and 1 (Outputs). 2048 kbit/s output data streams containing 32 8-bit channels synchronized to F0i. 5 6 RxD/ CSTi0 Received Data/Control Stream Input 0 (Input). When MPS is low, this pin receives serial microport data clocked in by the rising edge SCLK. When MPS is high, this pin receives a 2048 kbit/s serial TDM stream containing 32 8-bit channels, which are written into the Connect Memory locations corresponding to STo0. 6 7 TxD Transmit Data (Output). When MPS is low, serial microport data is clocked out on this pin by the falling edge of SCLK. When MPS is high this output is disabled. 7 9 SCLK/ CSTi1 Serial Microport Clock/Control Stream Input 1 (Input). When MPS is low, this pin receives a clock which is used to clock data to/from a microcontroller via a serial microport. When MPS is high, this pin receives a 2048 kbit/s serial TDM stream containing 32 8-bit channels, which are written into the Connect Memory locations corresponding to STo1. 810 VSS Power Input. Negative supply (ground). 911 CS Chip Select (Input). When MPS is low, a low on this pin enables the serial microport. A high on this pin disables RxD and tristates TxD. When MPS is high, this pin must be low. 10 12 C4i Serial TDM Clock (Input). This clock input is used to clock the TDM data into and out of the device and refreshes the internal dynamic RAM. The clock rate is 4.096 MHz and data is clocked in on the rising edge of C4i three-quarters of the way through a bit period. 11 14 F0i Frame Pulse (Input). This input is the frame synchronization pulse for the 2048 kbit/s serial TDM streams. It may be either active low stradling the frame boundary (ST-BUS) or active high at the beginning of timeslot 5 (GCI). 12 16 F0o Frame Pulse (Output). This pin outputs a frame pulse in the opposite format to F0i (GCI or ST-BUS) delayed or advanced by five channels. 13 17 MPS Microport Select (Input). When this pin is held low, the serial microport is in normal mode. When this pin is high, the microport is in serial bus mode. 14 18 IC Internal Connection. Tie to VSS for normal operation. 15 19 ODE Output Drive Enable (Input). When this pin is held high, the STo0 and STo1 output drivers function normally. When this pin is low, STo0 and STo1 are tristated. NB: When ODE is high, individual channels on STo0 and STo1 can be tristated under software control. 16 20 VDD Power Input. Positive supply. 3,8, 13,15 NC No Connection. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 PIN PLASTIC/SOIC STi0 STi1 STo0 STo1 RxD/CSTi0 TxD/NC SCLK/CSTi1 VSS VDD ODE IC MPS F0o F0i C4i CS 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 STi0 STi1 NC STo0 STo1 RxD/CSTi0 TxD/NC NC SCLK/CSTi1 VSS 20 PIN SSOP VDD ODE IC MPS NC F0i NC C4i CS F0o |
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Similar Description - MT8982-1 |
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