3-78

‡ Typical figures are at 25

Figure 17 - Timing Information for MPU Write

Characteristics

Sym

Min

Max

Units

Test Conditions

1

Delay between CS and E clock

0ns

2

Cycle time

205

ns

3

E Clock pulse width HIGH

145

ns

4

E Clock pulse width LOW

60

ns

5

Read/Write setup time

20

ns

6

Read/Write hold time

10

ns

7

Address setup time

20

ns

8

Address hold time

60

ns

9

Data setup time (write)

35

ns

10

Data hold time (write)

10

ns

11

E clock to valid data delay

145

ns

Test load circuit 1 (Fig. 26)

12

Data hold time (read)

10

60

ns

Test load circuit 3 (Fig. 26)

CS

E

CS

E

R/W

A0-A3

D0-D7

NOTE: The write cycle can be initiated either by the falling edge of CS or the rising edge of E clock whichever occurs last. Similarly

the cycle can be terminated by CS (rising edge) or E clock (falling edge) whichever occurs first. The timing relations are to be

referenced from the active edge initiating or terminating the cycle

E clock initiates and

terminates the write cycle

CS initiates and

terminates the write cycle