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MT8952B Datasheet(PDF) 20 Page - Mitel Networks Corporation |
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MT8952B Datasheet(HTML) 20 Page - Mitel Networks Corporation |
20 / 22 page MT8952B ISO-CMOS 3-80 † Timing is over recommended temperature & power supply voltages (VDD=5V±5%, VSS=0V, TA=–40 to 85°C). ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Figure 21 - RESET Timing Figure 22 - Serial Port Input and REOP, Output and TEOP Note: The frequency of the clock input CKi is assumed to be at the output bit rate. However, it can be at twice the bit rate in the Internal Timing Mode. AC Electrical Characteristics† - Serial Port, RESET, WD Timer and IRQ Release Time (Figures 19, 20, 21 and 22). Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym Min Typ‡ Max Units Test Conditions 1 Interrupt request release time tIRQR 120 ns Test load circuit 2 (Fig.26) 2 WD output delay HIGH to LOW tWDHL 135 ns Test load circuit 1 (Fig.26) 3 WD output delay LOW to HIGH tWDLH 135 ns Test load circuit 1 (Fig.26) 4 TEOP/REOP output delay tEOPD 110 ns Test load circuit 1 (Fig.26) 5 TEOP/REOP output hold time tEOPH 110 ns Test load circuit 1 (Fig.26) 6 CDSTo delay from CKi tSTOD 125 ns Test load circuit 1 (Fig.26) 7 CDSTi setup time tSTiS 20 ns 8 CDSTi hold time tSTiH 65 ns 9 RESET pulse width tRST 100 ns RST tRST CKi CDSTo TEOP CDSTi REOP End Flag or Abort Sequence Flag or Idle Sequence tSTOD tEOPD tEOPH tSTiS tSTiH tEOPD tEOPH |
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