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ACE9030MIWFP2Q Datasheet(PDF) 7 Page - Mitel Networks Corporation |
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ACE9030MIWFP2Q Datasheet(HTML) 7 Page - Mitel Networks Corporation |
7 / 39 page ACE9030 7 Parameter Min. Typ. Max. Unit Conditions CONTROL BUS Clock rate CL input 1008 kHz Clock duty cycle CL input 40 50 60 % t DS, input data set-up time 80 ns See Fig. 7 t DH, input data hold time 80 ns See Fig. 7 t CWL, tCWH, CL input pulse width (to bus logic) 400 600 ns See Fig. 7 t CL, delay time, clock to latch 440 ns See Fig. 7 t LW, latch pulse high time 230 ns See Fig. 7 t LH, delay time, latch to clock 220 ns See Fig. 7 t DSO, output data set-up time 80 ns See Fig. 8 t DHO, output data hold time 80 ns See Fig. 8 t ZS, DATA line available to ACE9030 80 1200 ns See Fig. 8 t ZH, DATA line released by ACE9030 80 1200 ns See Fig. 8 t CD, delay from received message to 4 4 cycles See Figs. 8 and 10 transmitted response of CL Rise and Fall times, all digital inputs: 50 ns DIGITAL OUTPUTS DOUT0 and 1 On time to V DD – 0·2 V 100 µs 100 nF load and from DOUT0 and 1 Off time to > 1 M Ω 100 µs LATCHB rising edge DOUT5, 6 and 7 rise and fall times 10 µs 30 pF load and to D.C. DOUT8 rise and fall time 10 µs specification noise A to D CONVERTER Lowest transition, 0000 0000 to 0000 0001 0·07 0·15 0·23 V Bandgap multiplier Highest transition, 1111 1110 to 1111 1111 3·35 3·45 3·55 V correctly trimmed ADC conversion time (20 cycles of CL) 20 µs CL = 1008 kHz Input scanning rate (CL ÷ 40) 25·2 kHz CL = 1008 kHz Integral Non-linearity – 1 + 1 LSB Differential Non-linearity – 0·8 + 0·8 LSB Power supply sensitivity 3 LSB/0.3V 0 to 10 kHz CRYSTAL OSCILLATOR Start-up time of crystal oscillator 5 ms Crystal effective series resistance (ESR) 25 Ω Power dissipation in crystal 50 150 µW D to A CONVERTERS Full scale output level, DAC1, DAC2 & DAC3 3·35 3·45 3·55 V Bandgap multiplier Zero scale output level, DAC1 1·0 1·2 V trimmed to nominal Zero scale output level, DAC2 & DAC3 0·3 0·5 V reference voltage Integral Non-linearity – 1 + 1 LSB Differential Non-linearity – 0·5 + 0·5 LSB Output wideband and clock noise: 50 Hz to 1·1 MHz, flat integration 3 mV rms Power supply rejection ratio 30 dB 50 Hz to 25 kHz. Settling time to within 10% of end of step 6 µs DAC1 and DAC2 (DAC3 with external 15 k Ω resistor) 10 pF load Output load capacitance, DAC1 and DAC2 100 nF Output load capacitance, DAC3 30 pF To guarantee stability Internal series resistor, DAC1 and DAC2 7 15 40 k Ω DAC3 output current, sink or source 1·0 mA ELECTRICAL CHARACTERISTICS These characteristics apply over these ranges of conditions (unless otherwise stated): T AMB = – 40 °C to + 85 °C, VDD = + 3·6 to + 5·0 V, GND ref. = VSS A.C. Characteristics |
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