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NOA1312CUTAG Datasheet(PDF) 3 Page - ON Semiconductor |
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NOA1312CUTAG Datasheet(HTML) 3 Page - ON Semiconductor |
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3 / 16 page  NOA1312 http://onsemi.com 3 Table 3. OPERATING RANGES Rating Symbol Min Typ Max Unit Power supply voltage VDD 2.4 3.0 3.6 V Power supply current IDD 140 240 mA Quiescent supply current (Note 3) IDDqs 12 800 nA Low level input voltage VIL −0.2 0.3 VDD V High level input voltage (Note 4) VIH 0.7 VDD VDD + 0.2 V Hysteresis of SCL & SDA Schmitt trigger inputs (VDD > 2 V) Vhys 0.05 VDD V Low level output voltage (open drain) at 3 mA sink current (SDA, INT) VOL 0 0.4 V Output low current (SDA, INT) IOL 3 − mA Output fall time from VIHmin to VILmax with a bus capacitance, Cb from 10 pF to 250 pF (Note 4) tof − − 250 ns Input current of IO pin with an input voltage between 0.1 VDD and 0.9 VDD II −10 10 mA Capacitance for IO pin (Note 4) Cb 10 pF Operating free−air temperature range TA −40 85 °C 3. Current dissipation when in Power Down mode. 800 nA power down current at 85°C (see Figure 14). 4. Cb = capacitance of one bus line, maximum value including all parasitic capacitances should be less than 250 pF. Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over 2.4 V < VDD < 3.6 V, −40°C < TA < 85°C, 10 pF < Cb < 100 pF) (Note 5) Parameter Symbol Standard Mode Fast Mode Unit Min Max Min Max SCL clock frequency fSCL 10 100 100 400 kHz Hold time after repeated start condition. After this period, the first clock pulse is generated. tHD;STA 4.0 − 0.6 − mS Low period of SCL clock tLOW 4.7 1.3 mS High period of SCL clock tHIGH 4.0 0.6 mS Set−up time for repeated START condition tSUSTA 4.7 − 0.6 − mS SDA Data hold time tHDDAT 0 3.45 0 0.9 mS SDA Data set−up time tSUDAT 250 − 100 − nS Rise time of both SDA and SCL (input signals) (Note 6) tr 5 1000 20 + 0.1Cb 300 nS Fall time of both SDA and SCL (input signals) (Note 6) tf 5 300 20 + 0.1Cb 300 nS Set−up time for STOP condition tSUSTO 4.0 − 0.6 − mS Bus free time between STOP and START condition tBUF 4.7 − 1.3 − mS Capacitive load for each bus line Cb − 250 − 250 pF Noise margin at the low level for each connected device (including hysteresis) VnL 0.1 VDD − 0.1 VDD − V Noise margin at the high level for each connected device (including hysteresis) VnH 0.2 VDD − 0.2 VDD − V Parameter Symbol Typ Typ Unit Internal Oscillator Frequency fosc 1 1 MHz 5. Refer to Figure 3 for more information on AC characteristics 6. The rise time and fall time are measured with a pull−up resistor Rp = 1 kW and Cb of 250 pF (including all parasitic capacitances). The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This allows series protection resistors (Rs) to be connected between the SDA/SCL pads and the SDA/SCL bus lines without exceeding the maximum specified tf. |
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