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NOA2301W Datasheet(PDF) 4 Page - ON Semiconductor |
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NOA2301W Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 19 page NOA2301W www.onsemi.com 4 Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over 2.3 V < VDD < 3.6 V, 1.7 V < VDD_I2C < 1.9 V, −40 °C < TA < 80°C, 10 pF < Cb < 100 pF) (See Note 4) Parameter Symbol Min Typ Max Unit LED pulse current ILED_pulse 10 160 mA LED pulse current step size ILED_pulse_step 5 mA LED pulse current accuracy ILED_acc −20 +20 % Interval Timer Tolerance Tolf_timer −35 +35 % Edge Triggered Interrupt Pulse Width PWINT 50 mS SCL clock frequency fSCL_std 10 100 kHz fSCL_fast 100 400 fSCL_hs 100 3400 Hold time for START condition. After this period, the first clock pulse is generated. THD;STA_std 4.0 − mS tHD;STA_fast 0.6 − tHD;STA_hs 0.160 − Low period of SCL clock tLOW_std 4.7 − mS tLOW_fast 1.3 − tLOW_hs 0.160 − High period of SCL clock tHIGH_std 4.0 − mS tHIGH_fast 0.6 − tHIGH_hs 0.060 − SDA Data hold time tHD;DAT_d_std 0 3.45 mS tHD;DAT_d_fast 0 0.9 tHD;DAT_d_hs 0 0.070 SDA Data set−up time tSU;DAT_std 250 − nS tSU;DAT_fast 100 − tSU;DAT_hs 10 Rise time of both SDA and SCL (input signals) (Note 5) tr_INPUT_std 20 1000 nS tr_INPUT_fast 20 300 tr_INPUT_hs 10 40 Fall time of both SDA and SCL (input signals) (Note 5) tf_INPUT_std 20 300 nS tf_INPUT_fast 20 300 tf_INPUT_hs 10 40 Rise time of SDA output signal (Note 5) tr_OUT_std 20 300 nS tr_OUT_fast 20 + 0.1 Cb 300 tr_OUT_hs 10 80 Fall time of SDA output signal (Note 5) tf_OUT_std 20 300 nS tf_OUT_fast 20 + 0.1 Cb 300 tf_OUT_hs 10 80 Set−up time for STOP condition tSU;STO_std 4.0 − mS tSU;STO_fast 0.6 − tSU;STO_hs 0.160 − 4. Refer to Figure 2 and Figure 3 for more information on AC characteristics. 5. The rise time and fall time are dependent on both the bus capacitance (Cb) and the bus pull−up resistor Rp. Max and min pull−up resistor values are determined as follows: Rp(max) = tr (max)/(0.8473 x Cb) and Rp(min) = (Vdd_I2C – Vol(max))/Iol. 6. Cb = capacitance of one bus line, maximum value of which including all parasitic capacitances should be less than 100 pF. Bus capacitance up to 400 pF is supported, but at relaxed timing. |
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