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NCP5424ADR2 Datasheet(PDF) 10 Page - ON Semiconductor |
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NCP5424ADR2 Datasheet(HTML) 10 Page - ON Semiconductor |
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10 / 20 page  NCP5424A http://onsemi.com 10 Out−of−Phase Synchronization In out−of−phase synchronization, the turn−on of the second channel is delayed by half the switching cycle. This delay is supervised by the oscillator, which supplies a clock signal to the second channel which is 180 ° out of phase with the clock signal of the first channel. The advantages of out−of−phase synchronization are many. Since the input current pulses are interleaved with one another, the overlap time is reduced. The effect of this overlap reduction is to reduce the input filter requirement, allowing the use of smaller components. In addition, since peak current occurs during a shorter time period, emitted EMI is also reduced, thereby reducing shielding requirements. Overvoltage Protection Overvoltage Protection (OVP) is provided as a result of the normal operation of the V2 control method and requires no additional external components. The control loop responds to an overvoltage condition within 150 ns, turning off the upper MOSFET and disconnecting the regulator from its input voltage. This results in a crowbar action to clamp the output voltage preventing damage to the load. The regulator remains in this state until the overvoltage condition ceases. Input Current Sharing In contemporary high−end applications, part of a system may require more power than is available from one supply. The NCP5424A dual controller can address this requirement in two ways. In many cases, it is sufficient to be able to set the input power sharing as a ratio so that one source always supplies a certain percentage of the total. This is achieved by having the Error Amplifier inputs from Slave side, Controller Two, brought to external pins so its’ reference is available. Current information from the Master, Controller One, provides a reference for the Slave. Current information from the Slave is fed back to the error amplifier’s inverting input. The Slave will try to adjust its current to match the current information fed to its reference input from the Master. If this information is 1/2 the voltage developed across the Master’s output inductor, the Slave will run at half current and supply a percentage, nominally 33% in this case, of the total current. In other applications however, the user may not only wish to draw a percentage of power from one source, but also may need to limit the power drawn from that source. The Slave has a Cycle−By−Cycle current limit. In this case, the Slave can be programmed to budget the maximum input power. For example, a designer may wish to draw equal amounts of power from two 5−volt sources, but only 2 amps are available from one of the supplies. In this case, the dual controller will draw equally from the two sources up to a total of 4 amps. At this point, the Slave controller goes into current limit and draws no more than its preset budget. The Master continues to supply the remaining output current up to the maximum that the application requires. Current limiting The NCP5424A has two current limit amplifiers with internal 70 mV offsets. These differential amplifiers have a common mode range from zero to 5.5 volts, and low input bias currents. Both amplifiers share a common negative input, which restricts dual current limiting to single output mode applications. In dual output mode applications, independent current limits are not supported. The preferred method of current sensing is inductor sensing (see following section). However, alternate means of current sensing, such as Rds(on), or sense resistors, are also supported. Once a voltage greater that 70 mV is applied to the current limiting amplifier; it will produce an output that resets the output RS flip flop. This event terminates the PWM pulse for that cycle, limiting the energy delivered to the load on a cycle−by−cycle basis. An advantage of this current limiting scheme is that the chip will resume normal operation within one cycle after the overcurrent condition clears. A second benefit of PWM pulse width limiting occurs in input power sharing applications, where one channel of the controller can be current limited while the other channel supplies the remaining current in excess of that level. It is important to realize that in current limit the feedback path to the error amplifier is effectively opened. The error amplifier output will start to drift high in response to the condition of output voltage low with respect to its reference. When the part comes out of current limit, the error amplifier output voltage will be at the wrong quiescent voltage, and will immediately start to recover. If the response of the output filter is faster than the response of the error amplifier, an undesirable positive overshoot can occur in the output. This phenomenon is not unique to the NCP5424A, but is more pronounced because the response of the error amplifier with a large compensation capacitor is intentionally slow. This effect can be mitigated by the addition of a voltage divider and diode clamp connected to limit Comp pin voltage excursions. The nominal voltage at the Comp pin is the sum of the reference voltage, the 0.45 Volt offset, and the ramp voltage. Clamping the Comp voltage 0.2 volts above the sum of these voltages keeps the recovery of the Error amplifier response fast enough to eliminate output overshoot. An additional 8K resistor connected between the channel 1 and channel 2 Comp pins will prevent overshoot of the Channel one output during recovery from a Channel 1 overload. Output Enable On/Off control of the regulator outputs can be implemented by pulling the COMP pins low. The COMP pins must be driven below the 0.40 V PWM comparator offset voltage in order to disable the switching of the GATE drivers. |
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