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M37280MF Datasheet(PDF) 42 Page - Mitsubishi Electric Semiconductor |
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M37280MF Datasheet(HTML) 42 Page - Mitsubishi Electric Semiconductor |
42 / 178 page 42 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER M37280MF–XXXSP, M37280MK–XXXSP M37280EKSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some paramentic limits are subject to change. Rev. 1.0 12.6.8 START/STOP Condition Detect Condi- tions The START/STOP condition detect conditions are shown in Figure 12.6.11 and Table 12.6.3. Only when the 3 conditions of Table 12.6.3 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” is generated to the CPU. Fig. 12.6.11 START Condition/STOP Condition Detect Timing Dia- gram Standard Clock Mode 6.5 µs (26 cycles) < SCL release time 3.25 µs (13 cycles) < Setup time 3.25 µs (13 cycles) < Hold time High-speed Clock Mode 1.0 µs (4 cycles) < SCL release time 0.5 µs (2 cycles) < Setup time 0.5 µs (2 cycles) < Hold time Table 12.6.3 START Condition/STOP Condition Detect Conditions Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the num- ber of φ cycles. Hold time Setup time SCL SDA (START condition) SDA (STOP condition) SCL release time Hold time Setup time 12.6.9 Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective ad- dress communication formats is described below. (1) 7-bit Addressing Format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to “0.” The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00F716) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 12.6.12, (1) and (2). (2) 10-bit Addressing Format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to “1.” An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, an address com- parison between the RBW bit of the I2C address register (address 00F716) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00F816) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00F616), make an address comparison between the sec- ond-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I2C address register (address 00F716) to “1” by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00F716). For the data transmis- sion format when the 10-bit addressing format is selected, refer to Figure 12.6.12, (3) and (4). |
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