NB3N106K

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2

Figure 2. Pinout Configuration (Top View)

1

2

3

4

5

6

78

9

10

11

12

18

17

16

15

14

13

24

23

22

21

20

19

IREF

VTCLK

CLK

CLK

VTCLK

GND

VCC

Q2

Q2

Q3

Q3

VCC

NB3N106K

Exposed Pad (EP)

Table 1. PIN DESCRIPTION

Pin

Name

I/O

Description

1

IREF

Use the IREF pin to set the output drive. Connect a 475 W RREF resistor from the

IREF pin to GND to produce 2.6 mA of IREF current. A current mirror multiplies

IREF by a factor of 5.4x to force 14 mA through a 50 W output load. See Figures 6

and 12.

2, 5

VTCLK,

VTCLK

−

Internal 50 W Termination Resistor connection Pins. In the differential configuration

when the input termination pins are connected to the common termination voltage,

and if no signal is applied then the device may be susceptible to self−oscillation.

3

CLK

LVPECL,

HCSL, LVDS

Input

Clock (TRUE) Input

4

CLK

LVPECL,

HCSL, LVDS

Input

Clock (INVERT) Input

8, 10, 14, 16, 20,

22

Q[5−0]

HCSL or

LVDS (Note 1)

Output

Output (INVERT) (Note 1)

9, 11, 15, 17, 21,

23

Q[5−0]

HCSL or

LVDS

(Note 1)

Output

Output (TRUE) (Note 1)

6

GND

−

Supply Ground. GND pin must be externally connected to power supply to

guarantee proper operation.

7, 12, 13, 18, 19,

24

−

supply to guarantee proper operation.

Exposed Pad

EP

GND

Exposed Pad. The thermally exposed pad (EP) on package bottom (see case

drawing) must be attached to a sufficient heat−sinking conduit for proper thermal

operation and electrically connected to the circuit board ground (GND).

1. Outputs can also interface to LVDS receiver when terminated per Figure 11.