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SZESD7205M3T5G Datasheet(PDF) 2 Page - ON Semiconductor |
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SZESD7205M3T5G Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 8 page ESD7205, SZESD7205 www.onsemi.com 2 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM Working Peak Reverse Voltage IR Maximum Reverse Leakage Current @ VRWM VBR Breakdown Voltage @ IT IT Test Current *See Application Note AND8308/D for detailed explanations of datasheet parameters. Uni−Directional TVS IPP IF V I IR IT VRWM VC VBR VF ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage VRWM I/O Pin to GND 5.0 V Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.2 6.0 8.0 V Reverse Leakage Current IR VRWM = 5.0 V, I/O Pin to GND 1 mA Clamping Voltage (Note 1) VC IEC61000−4−2, ±8 kV Contact See Figures 3 and 4 Clamping Voltage TLP (Note 2) VC IPP = 8 A IPP = 16 A IPP = −8 A IPP = −16 A 10 12.5 −4.0 −8.0 V Junction Capacitance Match DCJ VR = 0 V, f = 1 MHz between I/O1 to GND and I/O 2 to GND 5 10 % Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins 0.2 0.35 pF Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.4 0.55 pF 3dB Bandwidth fBW RL = 50 W 5 GHz 1. For test procedure see Figures 5 and 6 and application note AND8307/D. 2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. |
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