NB3N51032DTR2G datasheet(5/13 Pages) ONSEMI

Part #	NB3N51032DTR2G

Description	Dual HCSL/LVDS Clock Generator

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Manufacturer	ONSEMI [ON Semiconductor]

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NB3N51032

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5

Table 7. AC CHARACTERISTICS (VDD = 3.3 V ±5%, GND = 0 V, TA = −40°C to +85°C; Note 9)

Symbol

Characteristic

Min

Typ

Max

Unit

fCLKIN

Clock/Crystal Input Frequency

25

MHz

fCLKOUT

Output Clock Frequency

25

200

MHz

FNOISE

Phase−Noise Performance

fCLKOUT = 100 Mhz

@ 100 Hz offset from carrier

@ 1 kHz offset from carrier

@ 10 kHz offset from carrier

@ 100 kHz offset from carrier

@ 1 MHz offset from carrier

@ 10 MHz offset from carrier

−88

−118

−131

−132

−144

−155

dBc/Hz

tJITTER

Period Jitter Peak−to−Peak (Note 10)

fCLKOUT = 200 Mhz

Period Jitter RMS (Note 10)

fCLKOUT = 200 MHz

Cycle−Cycle RMS Jitter (Note 11)

fCLKOUT = 200 MHz

Cycle−to−Cycle Peak to Peak Jitter (Note 11)

fCLKOUT = 200 MHz

10

1.5

2.0

20

3.0

5.0

35

ps

tJIT(F)

Phase RMS Jitter, Integration Range 12 kHz to 20 MHz

0.5

ps

fMOD

Spread Spectrum Modulation Frequency

30

31.5

33.33

kHz

SSCRED

Spectral Reduction, fCLKOUT of 100 MHz with −0.5% spread, 3rd Harmonic

(Note 12)

−10

dB

tSKEW

Within Device Output to Output Skew

40

ps

Eppm

Frequency Synthesis Error, All Outputs

0

ppm

tSPREAD

Spread Spectruction Transition Time

(Stablization Time After Spread Spectrum Changes)

7

30

ms

tOE

Output Enable/Disable Time (Note 13)

10

ms

tDUTY_CYCLE

Output Clock Duty Cycle (Measured at cross point)

45

50

55

%

tR

Output Risetime (Measured from 175 mV to 525 mV, Figure 11)

175

700

ps

tF

Output Falltime (Measured from 525 mV to 175 mV, Figure 11)

175

700

ps

DtR

Output Risetime Variation (Single−Ended)

125

ps

DtF

Output Falltime Variation (Single−Ended)

125

ps

Stabilization

Time

Stabilization Time From Powerup VDD = 3.3 V

3.0

ms

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

9. VDDXD and VDDODA power pins must be shorted to power supply voltage VDD and GNDXD and GNDODA ground pins must be shorted

to power supply ground GND. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 49.9

W, with test load capacitance of 2 pF and current biasing resistor set at 475 W. See Figure 9. Guaranteed by characterization.

10. Sampled with 10000 cycles.

11. Sampled with 1000 cycles.

12. Spread spectrum clocking enabled.

13. Output pins are tri−stated when OE is asserted LOW. Output pins are driven differentially when OE is HIGH.

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