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ADP3207A Datasheet(PDF) 16 Page - ON Semiconductor |
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ADP3207A Datasheet(HTML) 16 Page - ON Semiconductor |
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16 / 28 page  ADP3207A Rev.1 | Page 16 of 28 | www.onsemi.com function alive even after OVP latch-off. During OVP latch-off, if the CSREF pin voltage drops below −300mV, then all low-side MOSFETs are turned off by setting both DCM and OD low. The DCM pin and the OD pin are set high again when CSREF voltage recovers above −100 mV. OUTPUT ENABLE AND UVLO The VCC supply voltage to the controller must be higher than the UVLO upper threshold, and the EN pin must be higher than its logic threshold so the ADP3207A can begin switching. If the VCC voltage is less than the UVLO threshold, or the EN pin is logic low, then the ADP3207A is in shutdown. In shutdown, the controller holds the PWM outputs at ground, shorts the SS pin capacitor to ground, and drives DCM and OD pins low. Proper power supply sequencing during start-up and shutdown of the ADP3207A must be adhered to. All input pins must be at ground prior to applying or removing VCC. All output pins should be left in high impedance state while VCC is off. THERMAL THROTTLING CONTROL The ADP3207A includes a thermal monitoring circuit to detect if the temperature of the variable resistor (VR) has exceeded a user-defined thermal throttling threshold. The thermal monitoring circuit requires an external resistor divider connected between the VCC pin and GND. The divider consists of an NTC thermistor and a resistor. To generate a voltage that is proportional to temperature, the midpoint of the divider is connected to the TTSENSE pin. Whenever the temperature trips the set alarm threshold, an internal comparator circuit compares the TTSENSE voltage to a half VCC threshold and outputs a logic level signal at the VRTT output. The VRTT output is designed to drive an external transistor that, in turn, provides the high current, open-drain VRTT signal that is required by the IMVP-6 specification. When the temperature is around the set alarm point, the internal VRTT comparator has a hysteresis of about 100 mV to prevent high frequency oscillation of VRTT. The TTSENSE pin also serves the function of disabling OVP. In extreme heat, users should make sure that the TTSENSE pin voltage remains above 1 V if OVP is desired. POWER MONITOR OUTPUT The ADP3207A provides power monitoring signal on its PMON pin. The PMON output is a PWM signal at about 300 kHz frequency. The magnitude of the PMON PWM signal is twice the voltage of CSREF pin, and the duty cycle of the PMON PWM is proportional to the total inductor current. Therefore, after the RC filter, the averaged PMON signal is proportional to the total output power. See the Application Information section for the signal size. Table 6. VID Code Table VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output (V) 0 0 0 0 0 0 0 1.5000 0 0 0 0 0 0 1 1.4875 0 0 0 0 0 1 0 1.4750 0 0 0 0 0 1 1 1.4625 0 0 0 0 1 0 0 1.4500 0 0 0 0 1 0 1 1.4375 0 0 0 0 1 1 0 1.4250 0 0 0 0 1 1 1 1.4125 0 0 0 1 0 0 0 1.4000 0 0 0 1 0 0 1 1.3875 0 0 0 1 0 1 0 1.3750 0 0 0 1 0 1 1 1.3625 0 0 0 1 1 0 0 1.3500 0 0 0 1 1 0 1 1.3375 0 0 0 1 1 1 0 1.3250 0 0 0 1 1 1 1 1.3125 0 0 1 0 0 0 0 1.3000 0 0 1 0 0 0 1 1.2875 0 0 1 0 0 1 0 1.2750 0 0 1 0 0 1 1 1.2625 0 0 1 0 1 0 0 1.2500 0 0 1 0 1 0 1 1.2375 0 0 1 0 1 1 0 1.2250 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output (V) 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.0750 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.0500 0 1 0 0 1 0 1 1.0375 0 1 0 0 1 1 0 1.0250 0 1 0 0 1 1 1 1.0125 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 |
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