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ADP3207 Datasheet(PDF) 24 Page  ON Semiconductor 

ADP3207 Datasheet(HTML) 24 Page  ON Semiconductor 
24 / 29 page ADP3207 Rev. 1  Page 24 of 29  www.onsemi.com CR is the internal ramp capacitor value. RR is an external resistor on the RAMPADJ pin to set the internal ramp magnitude. Because RR = 280 kΩ, the following resistance sets up 300 kHz switching frequency in RPM operation. Ω k 6 . 80 500 kHz 300 pF 7 Ω k 280 150 . 1 ) 061 . 0 1 ( 2 . 0 V 0 . 1 V 150 . 1 Ω k 237 2 = Ω − × × × − × × + × = RPM R CURRENTLIMIT SETPOINT To select the currentlimit setpoint, we need to find the resistor value for RLIM. The currentlimit threshold for the ADP3207 is set with a 1.7 V source (VLIM) across RLIM with a gain of 13 mV/μA. RLIM can be found using the following equation: O LIM LIM LIM LIM R I V A R × × = (25) For values of RLIM greater than 500 kΩ, the current limit may be lower than expected, so some adjustment of RLIM may be needed. Here, ILIM is the average current limit for the output of the supply. In this example, if choosing 55 A for ILIM, RLIM is 190 kΩ, which is close to a standard 1% resistance of 191 kΩ. The perphase current limit described earlier has its limit determined by the following: 2 ) ( ) ( R MAX DS D BIAS R MAX COMP PHLIM I R A V V V I + × − − ≅ (26) For the ADP3207, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.0 V, and the current balancing amplifier gain (AD) is 5. Using a VR of 0.55 V, and a RDS(MAX) of 3.8 mΩ (lowside onresistance at 150°C) results in a perphase limit of 85 A. Although this number seems high, this current level can only be reached with a absolute short at the output and the currentlimit latchoff function shutting down the regulator before overheating occurs. This limit can be adjusted by changing the ramp voltage VR. However, users should not set the perphase limit lower than the average perphase current (ILIM/n). There is also a perphase initial dutycycle limit at maximum input voltage: R BIAS MAX COMP MIN LIM V V V D D − × = ) ( (27) For this example, the dutycycle limit at maximum input voltage is found to be 0.25 when D is 0.061. FEEDBACK LOOP COMPENSATION DESIGN Optimized compensation of the ADP3207 allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate. This ensures the optimal positioning and minimizes the output decoupling. With the multimode feedback structure of the ADP3207, users need to set the feedback compensation to make the converter output impedance work in parallel with the output decoupling. Several poles and zeros are created by the output inductor and decoupling capacitors (output filter) that need to be compensated for. A typethree compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 28 to Equation 36 is intended to yield an optimal starting point for the design; some adjustments can be necessary to account for PCB and component parasitic effects (see the Tuning Procedure for ADP3207). The first step is to compute the time constants for all of the poles and zeros in the system () VID O X RT ID RT L DS D O E V R C n V D n L V V R R A R n R × × × × × − × × + × + × + × = 1 2 (28) () X O O X O X A R R R R L R R C T ' ' − × + − × = (29) ( ) X O X B C R R R T × − + = ' (30) E VID SW DS D RT C R V f R A L V T × ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × × − × = 2 (31) () O Z O X O Z X D R C R R C R C C T × + − × × × = ' 2 (32) where: R’ is the PCB resistance from the bulk capacitors to the ceramics. RDS is the total lowside MOSFET onresistance per phase. For this example, AD is 5, VRT = 1. 5 V, R’ is approximately 0.4 mΩ (assuming an 8layer motherboard) and LX is 250 pH for the four Panasonic SP capacitors. 
