Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ADP3207 Datasheet(PDF) 19 Page - ON Semiconductor

Part No. ADP3207
Description  CPU Synchronous Buck Controller
Download  29 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo 

ADP3207 Datasheet(HTML) 19 Page - ON Semiconductor

Zoom Inzoom in Zoom Outzoom out
 19 / 29 page
background image
ADP3207
Rev. 1 | Page 19 of 29 | www.onsemi.com
APPLICATION INFORMATION
The design parameters for a typical Intel IMVP6-compliant
CPU Core VR application are as follows:
Maximum input voltage (VINMAX) = 19 V
Minimum input voltage (VINMIN) = 7 V
Output voltage by VID setting (VVID) = 1.150 V
Maximum output current (IO) = 44 A
Load line slope (RO) = 2.1 mΩ
Maximum output current step (ΔIO) = 34.5 A
Maximum output thermal current (IOTDC) = 32 A
Number of phases (n) = 2
Switching frequency per phase (fSW) = 280 kHz
Duty cycle at maximum input voltage (DMIN) = 0.061
Duty cycle at minimum input voltage (DMAX) = 0.164
SETTING THE CLOCK FREQUENCY FOR PWM
MODE
In PWM mode operation, The ADP3207 uses a fixed-frequency
control architecture. The frequency is set by an external timing
resistor (RT). The clock frequency and the number of phases
determine the switching frequency per phase, which directly
relates to switching losses, and the sizes of the inductors and
input and output capacitors. In a 2-phase design, a clock
frequency of 560 kHz sets the switching frequency to 280 kHz
per phase. This selection represents a trade-off between the
switching losses and the minimum sizes of the output filter
components. To achieve a 560 kHz oscillator frequency at VID
voltage 1.150 V, RT has to be 237 k
Ω. Alternatively, the value for
RT can be calculated using
Ω
×
×
+
=
k
5
pF
16
V
0
.
1
SW
VID
T
f
n
V
R
(1)
where 16 pF and 25 k
Ω are internal IC component values. For
good initial accuracy and frequency stability, it is recommended
to use a 1% resistor.
SOFT-START AND CURRENT-LIMIT LATCH-OFF
DELAY TIMES
The soft-start and current-limit latch-off delay functions share
the SS pin. Consequently, these two parameters must be
considered together. The first step is to set CSS for the soft-start
ramp. This ramp is generated with a 8 μA internal current
source. The value for CSS can be set as
BOOT
SS
SS
V
t
C
×
=
μA
8
(2)
where:
VBOOT is the boot voltage for the CPU, defined in the IMVP-6
specification as 1.2 V.
tSS is the desired soft-start time, recommended to be below 3 ms
in the IMVP-6 specification.
Assuming a desired soft-start time of 2 ms,
CSS is 13.3 nF, with
the closest standard capacitance at 12 nF.
Once CSS has been chosen, the current-limit latch-off time is
equal to 7.2 ms according to the following calculation:
μA
2
V
2
.
1
SS
DELAY
C
t
×
=
(3)
PWRGD DELAY TIMER
The PWRGD delay, tCPU_PWRGD, is defined in the IMVP-6
specification as the time period between the CLKEN assertion
and the PWRGD assertion. It is programmed by a cap on the
PGDELAY pin.
V
9
.
2
μA
9
.
1
_
PWRGD
CPU
PGDLY
t
C
×
=
(4)
The IMVP-6 specifies that the PWRGD delay is between 3 ms
to 20 ms. Assuming 7 ms PWRGD delay is preferred, then
CPGDLY is 4.7 nF.
INDUCTOR SELECTION
The choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and conduction losses in the
MOSFETs. However, this allows the use of smaller-size inductors,
and for a specified peak-to-peak transient deviation, it allows
less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
requires larger size inductors and more output capacitance for
the same peak-to-peak transient deviation. In a multiphase
converter, the practical peak-to-peak inductor ripple current is
less than 50% of the maximum dc current in the same inductor.
Equation 5 shows the relationship between the inductance,
oscillator frequency, and peak-to-peak ripple current. Equation
6 can be used to determine the minimum inductance based on
a given output ripple voltage.
(
)
L
f
D
V
I
SW
MIN
VID
R
×
×
=
1
(5)
((
)) (
)
RIPPLE
SW
MIN
MIN
O
VID
V
f
D
D
n
R
V
L
×
×
×
×
×
1
1
(6)


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn