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ADP3207 Datasheet(PDF) 15 Page - ON Semiconductor

Part No. ADP3207
Description  CPU Synchronous Buck Controller
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com

ADP3207 Datasheet(HTML) 15 Page - ON Semiconductor

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Table 5 lists the source/sink current on the STSET pin for
various transitions. By charging/discharging the external
capacitor on the STSET pin, users actually program the voltage
slew rate on the STSET pin, and consequently, on the VCORE
output. For example, a 750 pF STSET capacitor leads to a
10 mV/s VCORE slew rate appropriate for a fast exit from deeper
sleep, and to a ±3.3 mV/μs VCORE slew rate for a slow entry to, or
exit from, deeper sleep.
Table 5. Source/Sink Current of STSET
System Signals
VID Transient
Entrance to Deeper Sleep
Fast Exit from Deeper Sleep
Slow Exit from Deeper Sleep
Transient from VBOOT to VID
±2.5 μA
1 Do not care.
The ADP3207 compares the differential output of a current-
sense amplifier to a programmable current-limit setpoint to
provide current-limiting function. The nominal voltage on the
ILIMIT pin is 1.7 V. The current-limit threshold is set with a
resistor connected from the ILIMIT pin to GND. In multiphase
normal operating mode, the ILIMIT is internally scaled by
using a trimmed 12 k
Ω resistor to give a current-limit threshold
of 10 mV for each μA of ILIMIT current. For single-phase
operation, the current-limit threshold is scaled down even
further. The scaling factor is the user selected number of
phases. For example, a 3-phase design scales the current-limit
threshold to 3.3 mV/μA referred to single-phase operation; a 2-
phase design scales the current-limit threshold to 5 mV/μA also
referred to single-phase operation. During any mode of
operation, if the voltage difference between CSREF and
CSCOMP rises above the current-limit threshold, the internal
current-limit amplifier takes control over the internal COMP
voltage to maintain an average output current equal to the set
limit level.
During start-up when the output voltage is below 200 mV, a
secondary current limit is activated. This is necessary because
the voltage swing on CSCOMP cannot extend below ground.
The secondary current-limit circuit clamps the internal COMP
voltage and sets the internal compensation ramp termination
voltage at 1.5 V level. The clamp actually limits voltage drop
across the low side MOSFETs through the current balance
An inherent per phase current limit protects individual phases
in case one or more phases stop functioning because of a faulty
component. This limit is based on the maximum normal-mode
COMP voltage.
After a current limit is hit, or following a PWRGD failure, the
SS pin is discharged by an internal sink current of 2 μA. A
comparator monitors the SS pin voltage and shuts off the
controller when the voltage drops below about 1.65 V. Because
voltage ramp (2.9 V − 1.65 V = 1.25 V) and discharge current
(2 μA) are internally fixed, current-limit latch-off delay time
can be set by selecting the external SS pin capacitor.
The controller keeps cycling the phases during latch-off delay
time. If current overload is removed and PWRGD is recovered
before the 1.65 V threshold is reached, then the controller
resumes normal operation, and the SS pin voltage recovers to
2.9 V clamp level.
The latch-off can be reset by removing and reapplying VCC, or
by recycling the EN pin low and high for a short time. To
disable the current-limit latch-off function, an external pull-up
resistor can be tied from the SS pin to the VCC rail. The pull-up
current has to override the 2 μA sink current of the SS pin to
prevent the SS capacitor from discharging down to the 1.65 V
latch-off threshold.
The ADP3207 is designed to track dynamically changing VID
code. As a result, the converter output voltage, that is, the CPU
VCC voltage, can change without the need to reset either the
controller or the CPU. This concept is commonly referred to as
VID on-the-fly (VID OTF) transient. A VID-OTF can occur
either under light load or heavy load conditions. The processor
signals the controller by changing the VID inputs in LSB
incremental steps from the start code to the finish code. The
change can be either upwards or downwards steps.
When a VID input changes state, the ADP3207 detects the
change but ignores the new code for a minimum of time of
400 ns. This keep out is required to prevent reaction to false
code that can occur by a skew in the VID code while the 7-bit
VID input code is in transition. Additionally, the VID change
triggers a PWRGD masking timer to prevent a PWRGD failure.
Each VID change resets and retriggers the internal PWRGD
masking timer. As listed in Table 5, during any VID transient,
the ADP3207 forces a multiphase PWM mode regardless of
system input signals.
To protect the CPU load and output components of the
converter, the PWM outputs are driven low, DCM and OD are
driven high (that is, commanded to turn on the low-side
MOSFETs of all phases) when the output voltage exceeds an
OVP threshold of 1.7 V as specified by IMVP-6.
Turning on the low-side MOSFETs discharges the output
capacitor as soon as reverse current builds up in the inductors.
If the output overvoltage is due to a short of the high-side
MOSFET, then this crowbar action current limits the input

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