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ADP3207 Datasheet(PDF) 13 Page - ON Semiconductor

Part No. ADP3207
Description  CPU Synchronous Buck Controller
Download  29 Pages
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com

ADP3207 Datasheet(HTML) 13 Page - ON Semiconductor

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node side of the output inductors) are summed together by
using series summing resistors. The feedback resistor between
CSCOMP and CSSUM sets the gain of the current-sense
amplifier, and a filter capacitor is placed in parallel with this
resistor. The current information is then given as the voltage
difference between CSREF and CSCOMP. This signal is used
internally as a differential input for the current-limit
An additional resistor divider connected between CSREF and
CSCOMP with the midpoint connected to LLSET can be used
to set the load line required by the microprocessor specification.
The current information for load line setting is then given as
the voltage difference of CSREF − LLSET. The configuration in
the previous paragraph makes it possible for the load line slope
to be set independently of the current-limit threshold. In the
event that the current-limit threshold and load line do not have
to be independent, the resistor divider between CSREF and
CSCOMP can be omitted and the CSCOMP pin can be
connected directly to LLSET. To disable voltage positioning
entirely (that is, to set no load line), tie LLSET to CSREF.
To provide the best accuracy for current sensing, the CSA is
designed to have a low offset input voltage. In addition, the
sensing gain is set by an external resistor ratio.
To control the dynamic output voltage droop as a function of
the output current, the signal proportional to the total output
current is converted to a voltage that appears between CSREF
and LLSET. This voltage can be scaled to equal the droop voltage,
which is calculated by multiplying the droop impedance of the
regulator with the output current. The droop voltage is then
used as the control voltage of the PWM regulator. The droop
voltage is subtracted from the DAC reference output voltage
and determines the voltage positioning setpoint. The setup
results in an enhanced feed-forward response.
The ADP3207 has individual inputs for monitoring the current in
each phase. The phase current information is combined with an
internal ramp to create a current balancing feedback system
that is optimized for initial current accuracy and dynamic
thermal balance. The current balance information is
independent of the total inductor current information used for
voltage positioning described in the Active Impedance Control
Mode section.
The magnitude of the internal ramp can be set so the transient
response of the system becomes optimal. The ADP3207 also
monitors the supply voltage to achieve feed-forward control
whenever the supply voltage changes. A resistor connected from
the power input voltage rail to the RAMPADJ pin determines
the slope of the internal PWM ramp. Detailed information
about programming the ramp is given in the Ramp Resistor
Selection section.
External resistors can be placed in series with the SW2 and
SW3 pins to create an intentional current imbalance, if desired.
Such a condition can exist when one phase has better cooling
and supports higher currents than the other phase. Resistor
RSW2 and Resistor RSW3 (see the typical application circuit in
Figure 10) can be used to adjust thermal balance. It is
recommended to add these resistors during the initial design to
make sure placeholders are provided in the layout.
To increase the current in any given phase, users should make
RSW for that phase larger (that is, make RSW = 0 for the hottest
phase and do not change it during balance optimization).
Increasing RSW to 500
Ω makes a substantial increase in phase
current. Increase each RSW value by small amounts to achieve
thermal balance starting with the coolest phase.
When current limit is reached, the ADP3207 switches to full-
phase PWM mode, regardless of System Signal DRPSLP and PSI,
to avoid inrush current stress to the Phase 1 power stage.
A high gain bandwidth error amplifier is used for the voltage-
mode control loop. The noninverting input voltage is set via the
7-bit VID DAC. The VID codes are listed in Table 6. The
noninverting input voltage is offset by the droop voltage as a
function of current, commonly known as active voltage
positioning. The output of the error amplifier is the COMP pin,
which sets the termination voltage for the internal PWM ramps.
The negative input, FB, is tied to the output sense location
through a resistor, RB, for sensing and controlling the output
voltage at the remote sense point. The main loop compensation
is incorporated in the feedback network connected between FB
and COMP.
The power-good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open drain output that
can be pulled up through an external resistor to a voltage rail
that is not necessarily the same VCC voltage rail of the
controller. Logic high level indicates that the output voltage is
within the voltage limits defined by a window around the VID
voltage setting. PWRGD goes low when the output voltage is
outside of that window.
Following the IMVP-6 specification, PWRGD window is
defined as −300 mV below and +200 mV above the actual VID
DAC output voltage. For any DAC voltage below 300 mV, only
the upper limit of the PWRGD window is monitored. To
prevent false alarm, the power-good circuit is masked during
various system transitions, including any VID change and
entrance/exit out of deeper sleep. The duration of the PWRGD

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