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UCC28251 Datasheet(PDF) 16 Page - Texas Instruments |
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UCC28251 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 55 page  Enable Signal EN C1 R1 R2 UCC28251 EN Enable Signal (a) (b) UVLO EN 0.3V SS CLK 1 1 6 s C R m = 2 R 10 k > W UCC28251 SLUSBD8E – FEBRUARY 2013 – REVISED DECEMBER 2014 www.ti.com Feature Description (continued) A pulse signal may also be applied to the EN pin. Pulse-enable operation is shown on Figure 22. If the EN falling edge happens before the SS voltage reaches 0.3 V, the enable signal at EN pin is considered as a pulse. In this case, the next rising edge at EN pin disables the controller. If the falling edge of the first pulse at EN pin happens after SS rises to 0.3 V, the UCC28251 interprets the pulse enable as a level enable, and an external solution as shown on Figure 23 (a) can be used to reduce the pulse width. In this circuit, R2 is used to limit the current (especially the negative current) through the internal ESD cell. Figure 23 (b) illustrates the waveforms based on this solution. To prevent false trigger by noises, the pulse at the EN pin must be at least 2.25 V (minimum) high and 3 µs wide to be considered valid. Choose the R1, R2, and C values based on the following equations: Choose R2 based on the current limit requirement of under 0.1 mA . (1) Choose R1 arbitrarily but much smaller than R2 and choose C1 according to the time constant requirement to generate longer than 3-µs pulse. (2) If enable function is not used, pull EN pin to VREF. Figure 22. Pulse Enable at EN Pin Figure 23. An External Solution to Generate Enable Pulses for Pulse Enable 16 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: UCC28251 |
Similar Part No. - UCC28251_15 |
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Similar Description - UCC28251_15 |
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