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UCC28251 Datasheet(PDF) 43 Page - Texas Instruments

Part No. UCC28251
Description  UCC28251 Advanced PWM Controller With Prebias Operation
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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UCC28251 Datasheet(HTML) 43 Page - Texas Instruments

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UCC28251
www.ti.com
SLUSBD8E – FEBRUARY 2013 – REVISED DECEMBER 2014
10 Power Supply Recommendations
The COMP pin is the internal error amplifier’s output and also the input signal for PWM comparator. The
maximum input common voltage of the PWM comparator is 2.8 V. It is suggested to program the peak value of
RAMP to be lower than 2.3 V. Otherwise, the voltage of COMP pin should be clamp to be lower than 2.8 V by
external circuit in order to make the internal PWM comparator work properly. Please refer to COMP (3/10) for the
detail information.
11 Layout
11.1 Layout Guidelines
In order to increase the reliability and robustness of the design, it is recommended that the following layout
guidelines be met.
1. REF/EA+ The REF/EA+ pin is the non-inverting input of the error amplifier. For secondary side control, this
pin is used to set the reference of voltage loop which decides the output voltage. So it is important to keep it
clear from any of high voltage switching nodes. In addition, a decoupling capacitor located closely is
recommended. For primary side control, this pin needs to be connected to opto-coupler. it is important
minimize the loop area by running the EA+ signal and GND trace in parallel.
2. FB/EA- Please minimize the loop between FB/EA- and COMP and keep it clear from any of high voltage
switch nodes in order to avoid the noise injection into to the compensation loop.
3. COMP Please minimize the loop between FB/EA- and COMP and keep it clear from any of high voltage
switch nodes in order to avoid the noise injection into to the compensation loop.
4. GND As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon
the integrity of the ground return. Place all decoupling and filter capacitors as close as possible to the device
pins with short traces. The AGND pin is used as the return connection for the low-power signaling and
sensitive signal so it should be separated from the power stage ground to avoid ground bouncing.
5. VDD, VREF The VCC pin must be decoupled to GND by minimum 1-
μF ceramic capacitors placed close to
the pins.
6. SRA, SRB, OUTA, OUTB The SRA and SRB gate drive pins can be used to drive the inputs of gate driver or
to directly drive the primary winding of a gate-drive transformer or the to directly drive the input of isolator.
The tracks connected to these pins carry high dv/dt signals. Minimize noise pickup by routing them as far
away as possible from tracks connected to sensitive signal including EA+, EA-, COMP, VSENSE, RT,
RAMP/CS, ILIM, PS, SP.
7. HICC, SS, EN, OVP/OTP The connection track between the pin and external corresponding capacitor should
be short.
8. PS, SP, RT, VSENSE, RAMP/CS, ILIM These pins are noise sensitive so please allocate related resistor as
close as possible with the good ground connection.
Copyright © 2013–2014, Texas Instruments Incorporated
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