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UCC28251 Datasheet(PDF) 34 Page - Texas Instruments |
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UCC28251 Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 55 page 
HICC HICC 2.4 V 0.3 V T C 2.7 A - = ´ m OC(delay ) HICC 0.6 V T C 75 A = ´ m CLK OUTA OUTB ILIM 70ns 0.5V UCC28251 SLUSBD8E – FEBRUARY 2013 – REVISED DECEMBER 2014 www.ti.com Application Information (continued) 9.1.5 Cycle-by-Cycle Current Limit and Hiccup Mode Protection Cycle-by-cycle current limit is accomplished using the ILIM pin for both current mode control and voltage mode control. The input to the ILIM pin represents the primary current information. If the voltage sensed at ILIM pin exceeds 0.5 V, the current sense comparator terminates the pulse of output OUTA or OUTB. If the high current condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the current sense comparator instead of the PWM comparator. ILIM pin is pulled down by an internal switch at the rising edge of each clock cycle. This internal switch remains on for an additional 70 ns after OUTA or OUTB goes high to blank leading edge transient noise in the current sensing loop. This reduces the filtering requirements at the ILIM pin and improves the current sense response time. UCC28251 makes it possible to maintain flux balance during cycle-by-cycle current limit operation. The duty cycles of primary switches are always matched. If one switch duty cycle is terminated earlier because of current limiting, a matched duty cycle is applied to the other switch for the next half switching cycle, regardless of the current condition, as shown in Figure 43. This matched duty cycle helps to maintain volt-second balancing on the transformer and prevents the transformer saturation. Figure 43. Cycle-by-Cycle Current Limit Duty Cycle Matching Once the current limit is triggered, the 75-µA internal current source begins to charge the capacitor on HICC pin. If the current limit condition went away before HICC pin reaches 0.6 V, the device stops charge HICC capacitor and begins to discharge it with 2.7-µA current source. If the cycle-by-cycle current limit condition continues, HICC pin reachs 0.6 V, and all four outputs are shut down. The UCC28251 then enters hiccup mode. During hiccup mode, all four outputs keep low; SS pin is pulled to ground internally; a 2.7-µA current source continuously discharge HICC pin capacitor; until HICC pin voltage reaches 0.3 V. After that, HICC pin is discharged internally to get ready for the next HICC event. The whole converter starts with soft start after hiccup mode. The cycle-by-cycle current limit operation time before all four outputs shut down is programmed by external capacitor CHICC at HICC pin. The delay time can be calculated as: (26) The hiccup timer keeps all outputs being zero until the timer expires. The hiccup time THICC is calculated as: (27) As soon as the outputs are shut-down, SS pin is pulled down internally until the hiccup restart timer is reset after time duration THICC. The detailed illustration of HICCUP mode is shown in Figure 44. 34 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: UCC28251 |
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