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UCC28251 Datasheet(PDF) 31 Page - Texas Instruments |
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UCC28251 Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 55 page 
VSENSE VREF COMP FB/EA- REF /EA+ SS UCC28251 + + C SS C Z2 R Z2 C P1 + C Z3 R Z3 R O2 R O1 VOUT External Reference UCC28251 www.ti.com SLUSBD8E – FEBRUARY 2013 – REVISED DECEMBER 2014 Application Information (continued) Figure 40. Error Amplifier Setup for Primary-Side Control In the above configuration, the UCC28251 can only see the control loop feedback voltage, and cannot directly access the output voltage. The design of the soft-start time is critical to achieve optimal pre-biased start up performance. Some trial and error approaches are needed to achieve optimal performance. It is also important to choose the appropriate ramp amplitude. Refer to the ramp section discussion on the detailed design procedure for choosing ramp generation components. During soft start, regardless of the pre-biased condition, the output voltage is always lower than the regulation voltage, so that the feedback loop is always saturated. When the internal error amplifier is connected as a voltage follower, the COMP voltage follows the lower of the voltage on the RER/EA+ pin and the SS pin. Since the feedback loop is saturated, the COMP pin always follows the SS pin voltage, until the output voltage becomes regulated and the feedback voltage takes over. In this control method, the output voltage control loop is always saturated, and the controller soft starts the COMP pin voltage. Therefore, it is called open loop soft start. The primary-side switch duty cycle is controlled by the COMP pin voltage and by the RAMP/CS pin voltage. During soft start, the COMP pin voltage follows the SS pin as it is rising, so the primary-side switch duty cycle keeps increasing. When the output voltage becomes regulated, the feedback voltage becomes less than the SS pin voltage and the primary-side switch comes controlled by the control loop. For the primary-side control setup, because output voltage is not directly accessible, the internal pre-biased start up loop is disabled by connecting VSENSE to VREF. Instead, the internal ramp used to generate the synchronous rectifier duty cycle is fixed, with the peak voltage of 3 V. The duty cycle of the synchronous rectifier increases as the SS pin voltage increases. When the SS pin voltage reaches 2.9 V, the soft start is considered finished and the synchronous rectifier duty cycle becomes the complementary of the primary-side switch duty cycle, minus the programmed dead time. Because of different COMP pin voltages at different line voltages, the SR duty cycle generated by the internal ramp might be different than the complementary of the primary-side switch duty cycle (1-D). If the duty cycle is too large, the internal logic is able to limit the duty cycle to (1-D). However, if the duty cycle is too small, when the soft start is finished, the SR duty cycle has a sudden change, which will cause output voltage disturbance. To optimize the pre-biased start up performance, it is recommended that the duty cycle change at the end of soft start be as small as possible. 9.1.3 Voltage Mode Control and Input Voltage Feed-Forward For voltage mode control, a resistor RCS and a capacitor CCS are connected externally at RAMP/CS pin as shown in Figure 41. A ramp signal is generated on the RAMP/CS pin, at a rate of two times that of the switching frequency. The generated ramp signal is used to control the duty cycle for both the primary-side switches and secondary-side synchronous rectifiers. The ramp amplitude can be fixed or variable with the input voltage (input voltage feedforward). Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: UCC28251 |
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