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NB3V1106CDTR2G Datasheet(PDF) 6 Page - ON Semiconductor |
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NB3V1106CDTR2G Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 11 page NB3V110xC Series www.onsemi.com 6 PARAMETERS MEASUREMENT INFORMATION Figure 2. Test Load Circuit Figure 3. Application Load with 50 W Line Termination Figure 4. Application Load with Series Line Termination Figure 5. tDIS and tEN for Disable Low Figure 6. Output Skew tSk(o) Z= 50 O Ω R=50 W from Measurement Equipment V/2 DD LVCMOS Output V = 3.3 V, 2.5 V or 1.8 V DD C=2pF parasitic capacitance LVCMOS Output VDD R=100 W R=100 W Z= 50 O Ω parasitic input capacitance V = 3.3 V, 2.5V or 1.8 V DD LVCMOS Output Z= 50 O Ω RS = 10 Ohms (VDD = 3.3 V) RS = 5 Ohms (VDD = 2.5 V) RS = 0 Ohms (VDD = 1.8 V) parasitic input capacitance V = 3.3 V, 2.5 V or 1.8 V DD tDIS tEN VIN /2 OE Qn VIN /2 tsk(o) VDD /2 Qn+1 VDD /2 Qn tsk(o) |
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