NB3N853501EDTG datasheet(1/9 Pages) ONSEMI

Part #	NB3N853501EDTG

Description	Differential Clock Fanout Buffer Outputs

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Manufacturer	ONSEMI [ON Semiconductor]

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November, 2011 − Rev. 2

1

Publication Order Number:

NB3N853501E/D

NB3N853501E

3.3 V LVTTL/LVCMOS 2:1

MUX to 4 LVPECL

Differential Clock Fanout

Buffer Outputs with Clock

Enable and Clock Select

Description

The NB3N853501E is a pure 3.3 V supply 2:1:4 clock distribution

fanout buffer. Input MUX selects one of two LVCMOS/LVTTL CLK

lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using

LVCMOS/LVTTL levels. Outputs are LVPECL levels and are

synchronously enabled by CLK_EN using LVCMOS/LVTTL levels

(HIGH to enable outputs, LOW to disable output).

Features

• Four differential LVPECL Outputs

• Two Selectable LVCMOS/LVTTL CLOCK Inputs

• Up to 266 MHz Clock Operation

• Output to Output Skew: 30 ps (Max.)

• Device to Device Skew 250 ps (Max.)

• Propagation Delay 2.0 ns (Max.)

• Operating range: VCC = 3.3 ±5% V( 3.135 to 3.465 V)

• Additive Phase Jitter, RMS: 62 fs (Typ)

• Synchronous Clock Enable Control

• Industrial Temp. Range (−40°C to 85°C)

• Pb−Free TSSOP20 Package

• These are Pb−Free Devices

Figure 1. Simplified Logic Diagram

MARKING

DIAGRAM

A

= Assembly Location

L

= Wafer Lot

Y

= Year

W

= Work Week

G

= Pb−Free Package

http://onsemi.com

(Note: Microdot may be in either location)

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

ORDERING INFORMATION

TSSOP−20

DT SUFFIX

CASE 948E

NB3N

501E

ALYWG

G

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ON Semiconductor	NB3N853531E	251Kb / 9P	3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer March, 2012 ??Rev. 6
	NB3N853531EDTG	251Kb / 9P	3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer March, 2012 ??Rev. 6
	NB3N853531EDTR2G	251Kb / 9P	3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer March, 2012 ??Rev. 6

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