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NB3L83948C Datasheet(PDF) 5 Page - ON Semiconductor

Part # NB3L83948C
Description  2.5 V / 3.3 V Differential and LVTTL/LVCMOS 2:1 MUX
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB3L83948C Datasheet(HTML) 5 Page - ON Semiconductor

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NB3L83948C
http://onsemi.com
5
Table 6. AC CHARACTERISTICS VDD = VDDO = 3.3 $5% (3.135 to 3.465 V) or 2.5 $5% (2.375 to 2.625 V); VDD = 3.3 $5%
(3.135 to 3.465 V) and VDDO = 2.5 $5% (2.375 to 2.625 V) GND = 0 V, TA = −40°C to +85°C; (Note 5)
Symbol
Characteristic
Min
Typ
Max
Unit
Fmax
Maximum Operating Frequency
350
MHz
tPLH/tPHL
Propagation Delay, (crosspoint to VDDO/2) f ≤ 350 MHz
ns
3.3 V VDD = VDDO or 3.3 V VDD, 2.5 V VDDO; CLK/CLK to Qx
1.6
3.6
ns
3.3 V VDD = VDDO or 3.3 V VDD, 2.5 V VDDO; 3.3 V LVCMOS_CLK to Qx
1.0
3.0
2.5 V VDD = VDDO CLK/CLK to Qx
1.6
3.6
2.5 V VDD = VDDO LVCMOS_CLK to Qx
1.0
3.0
tPZL/tPZH
Output Enable Time OE to Qx
5
ns
tPLZ/tPHZ
Output Disable Time OE to Qx
5
ns
tSKEWDC
Duty Cycle Skew at VDD / 2
At 150 MHz; 3.3 V VDD = VDDO
At 200 MHz; 2.5 V VDD = VDDO
At 150 MHz; 2.5 V VDD = VDDO
45
45
40
55
55
60
%
tSKEWD−D
Device to Device Skew (similar condition)
CLK/CLK to Qx; CLK to Qx
1.0
ns
tSKEWO−O
Output to Output Skew Within A Device
25
100
ps
tS
Set−up Time to CLK tf
CLK_EN to CLK/CLK
CLK_EN to CLK
1.0
0.0
ns
tH
Hold Time to CLK tf
CLK/CLK to CLK_EN
CLK to CLK_EN
0.0
1.0
ns
tr/tf
Output rise and fall times
(0.8 V and 2.0 V) 3.3 V VDD = VDDO
(0.6 V and 1.8 V) or 3.3 V VDD, 2.5 VDDO
(0.6 V and 1.8 V) 2.5 V VDD = VDDO
1.0
1.0
1.3
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs loaded with 50
W to VTT (VDDO/2); see Figure 5. CLOCK input with 50% duty cycle. Measured at CLK/CLK crosspoint to Qx VDDO/2,
CLK VDDO/2 to Qx VDDO/2; see Figure 4.


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