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LM5039 Datasheet(PDF) 3 Page - Texas Instruments |
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LM5039 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 33 page  CS NC AGND RT COMP ACL SS HO LO PGND VCC SR1 SR2 REF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 EP LM5039 www.ti.com SNVS621D – FEBRUARY 2010 – REVISED MARCH 2013 Figure 2. WQFN-24 Package Top View PIN DESCRIPTIONS HTSSOP WQFN Name Description Application Information Pin Pin 1 23 RAMP Modulator ramp signal An external RC circuit from VIN sets the ramp slope. This pin is discharged at the conclusion of every cycle by an internal FET. Discharge is initiated by either the internal clock or the Volt • Second clamp comparator. 2 24 UVLO Line Under-Voltage Lockout An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4V threshold the VCC and REF regulators are enabled. When UVLO reaches the 1.25V threshold, the SS pin is released and the device enters the active mode. Hysteresis is set by an internal current source that sources 23 µA into the external resistor divider. 3 2 ACL Average Current Limit A capacitor connected between the ACL pin and GND operates as an integrator in the average current limit circuitry. The ACL capacitor is charged during current limit condition. As the ACL pin voltage rises, it terminates the cycle through the PWM comparator by pulling down the input of the comparator that is normally controlled through the COMP pin. This maintains equal pulse-widths in both the phases of the half-bridge and thereby maintains balance of the half-bridge capacitor voltages. 4 3 COMP Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is maximum with zero input current, while 1mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the AC voltage across the opto-coupler detector. 5 4 RT Oscillator Frequency Control and Normally regulated at 2V. An external resistor connected between Sync Clock Input. RT and AGND sets the internal oscillator frequency. The internal oscillator can be synchronized to an external clock with a frequency higher than the free running frequency set by the RT resistor. 6 5 AGND Analog Ground Connect directly to Power Ground. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM5039 |
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