HO

SR1

LO

SR2

T1

T2

T1

T2

LM5035

SNVS428H – JANUARY 2006 – REVISED OCTOBER 2015

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Feature Description (continued)

7.3.13 Synchronous Rectifier Control Outputs (SR1 and SR2)

Synchronous rectification (SR) of the transformer secondary provides higher efficiency, especially for low-output

for a MOSFET, significantly reduces rectification losses. In a typical application, the transformer secondary

winding is center tapped, with the output-power inductor in series with the center tap. The SR MOSFETs provide

the ground path for the energized secondary winding and the inductor current. Figure 14 shows that the SR2

MOSFET is conducting while HO enables power transfer from the primary. The SR1 MOSFET must be disabled

during this period, because the secondary winding connected to the SR1 MOSFET drain is twice the voltage of

the center tap. At the conclusion of the HO pulse, the inductor current continues to flow through the SR1

MOSFET body diode. Because the body diode causes more loss than the SR MOSFET, efficiency can be

improved by minimizing the T2 period, while maintaining sufficient timing margin over all conditions (component

tolerances, and so on) to prevent shoot-through current. When LO enables power transfer from the primary, the

SR1 MOSFET is enabled, and the SR2 MOSFET is off.

Figure 14. HO, LO, SR1 and SR2 Timing Diagram

During the time that neither HO nor LO is active, the inductor current is shared between both the SR1 and SR2

MOSFETs, which effectively shorts the transformer secondary and cancels the inductance in the windings. The

SR2 MOSFET is disabled before LO delivers power to the secondary to prevent power being shunted to ground.

The SR2 MOSFET body diode continues to carry about half the inductor current until the primary power raises

the SR2 MOSFET drain voltage and reverse biases the body diode. Ideally, dead-time T1 would be set to the

minimum time that allows the SR MOSFET to turn off before the SR MOSFET body diode starts conducting.

The SR1 and SR2 outputs are powered directly by the VCC regulator. Each output is capable of sourcing and

sinking 0.5-A peak. Typically, the SR1 and SR2 signals control SR MOSFET gate drivers through a pulse

transformer. The actual gate sourcing and sinking currents are provided by the secondary-side bias supply and

gate drivers.

The timing of SR1 and SR2 with respect to HO and LO is shown in Figure 14. SR1 is configured out-of-phase

with HO, and SR2 is configured out-of-phase with LO. The dead time between transitions is programmable by a

dead-time periods can be calculated using Equation 4 and Equation 5:

(4)

(5)

To set the minimum dead time (propagation delays only), the DLY pin must be left open or connected to the REF

pin. Any resistor value above 300 k

Ω connected between the DLY pin and AGND will also provide the minimum

period (approximately 5 ns).

18

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