P3MS650100H

http://onsemi.com

5

1.80

1.70

1.60

1.50

1.40

1.30

1.20

15

20

30

25

FREQUENCY (MHz)

Figure 2. Deviation vs. Frequency

1.80

15

20

30

25

1.70

1.60

1.50

1.40

1.30

1.20

1.10

1.00

35

40

50

45

55

60

FREQUENCY (MHz)

Figure 3. Deviation vs. Frequency

Noise Reduction Filter

CLKIN

VSS

VDD

2.2mF

C2

ModOUT

ModOUT

P3MS650100H

0.1mF

CLKIN

R

Rs

C1

VDDIN

Figure 4. Typical Application Schematic

Rs = Trace Impedance of PCB – Output Impedance of Device (Z0)

Note: Refer Pin Description table for Functionality details

4

1

23

PCB Layout Recommendation

For optimum device performance, following guidelines are recommended.

mF and a 2.2 mF decoupling capacitor should be

mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the

decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as

possible. All the VDD pins should have decoupling capacitors.