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NCS12802 Datasheet(PDF) 8 Page - ON Semiconductor |
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NCS12802 Datasheet(HTML) 8 Page - ON Semiconductor |
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8 / 21 page  NCS12802 http://onsemi.com 8 TYPICAL CHARACTERISTICS TA = +25°C, AVDD = 15 V, DVDD = 3.3 V, RL = 1.5 kW connected to Ground, CL = 200 pF, unless otherwise specified Figure 13. Analog Supply Current Histogram 7175 Units 2 2.8 3.6 4.4 5.2 6.4 6.8 2.4 3.2 4 4.8 6 5.6 1600 1200 800 400 0 APPLICATIONS INFORMATION POWER SUPLIES The NCS12802 has two power supplies: (AVDD, AGND) and (DVDD, DGND). DVDD is the digital power supply ranging from 2.3 V to 5.0 V and common to the timing controller and the device control interface. It provides the power supply for the digital circuitry inside the device. AVDD is the analog power supply and ranges from 9 V to 17.5 V offering a wide dynamic voltage range to the gamma reference generator particularly suitable for medium size and big size LCD panels. DVDD must be applied prior to or together with AVDD in order to prevent excessive power and current consumption (damage to the device may occur if AVDD left connected for an extended time without DVDD). BUFFERS The NCS12802 offers twelve programmable voltage references each with 10 bits resolution (1024−steps). Due to an I2C interface, a double−register structure per channel allowing data pre−loading , the NCS12802 allows fast, easy and dynamic updating of all the voltage references alternatively. The two−wire interface can be connected to standard (100 kHz), fast mode (400 kHz) or even a High Speed mode (3.4 MHz) I2C bus. Each buffer is capable of full−scale change in output voltage in less than 5 ms. All buffers can be driven to within 200 mV of the positive supply rail, and to within 0.07 V of the ground rail. The output can also switch full scale monitoring LD or BSKSEL pins in 5 ms. I2C SERIAL CONTROL INTERFACE INTRODUCTION SCL SDA Start Condition Stop Condition Command and/or data Address Byte Acknowledgment from slave b7 Ack b6 b5 b4 b3 b2 b1 b0 Figure 14. I2C Bus Format The NCS12802 communicates with the external timing controller using an I2C communication protocol. The NCS12802 is intended to operate also as a master controller depending on logic pins configuration. It is under the control of the timing controller (master device), which controls the clock (pin SCL) and the read or write operations through SDA. Both pins require pull up resistors on their path for proper operations. A communication is initiated by the master with a START condition toggling the SDA line from High to Low while SCL is High (Figure 14). The last bit (b0) in the slave address byte indicates if a write or read operation is intended. At the 9th clock pulse the device being addressed responds to the master by performing an Acknowledge (ACK) consisting to pull SDA at a Low level (ACK = SDA LOW right at the 9th clock pulse, see Figure 14). Each byte has to be followed by an acknowledge bit (Ack). |
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