TPS62150, TPS62150A, TPS62151, TPS62152, TPS62153

SLVSAL5C – NOVEMBER 2011 – REVISED OCTOBER 2015

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Feature Description (continued)

A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage follows this voltage in

both directions, up and down (see Application and Implementation).

8.3.3 Power Good (PG)

The TPS6215x has a built-in power-good (PG) function to indicate whether the output voltage has reached its

appropriate level or not. One use of the PG signal can be for start-up sequencing of multiple rails. The PG pin is

an open-drain output that requires a pullup resistor (to any voltage below 7 V). It can sink 2 mA of current and

maintain its specified logic-low level. It features PG = Low when EN, UVLO, or thermal shutdown turns the

device off and can actively discharge Vout (see Figure 39). VIN must remain present for the PG pin to stay Low.

8.3.4 Pin-Selectable Output Voltage (DEF)

Setting the DEF pin to High increases the output voltage of the TPS62150x devices by 5% above the nominal

allows adapting the power supply voltage to the variations of the application hardware. More detailed information

on voltage margining using the TPS62150x device is in SLVA489. The pin has an internally connected pulldown

resistor of about 400 k

Ω to ensure a proper logic level if the pin is high-impedance or floating after an initially Low

setting. Setting the pin High disconnects the resistor.

8.3.5 Frequency Selection (FSW)

To get high power density with a very small solution size, a high switching frequency allows the use of small

external components for the output filter. However, switching losses increase with the switching frequency. If

efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz

typical) by pulling FSW to High. It is mandatory to start with FSW = Low to limit inrush current, which connecting

FSW to VOUT or PG can accomplish. Running with lower frequency produces higher efficiency, but also creates

higher output-voltage ripple. Pull FSW to Low for high-frequency operation (2.5 MHz typical). To get low ripple

and full output current at the lower switching frequency, the recommended minimum inductor value is 2.2 µH. An

application can change the switching frequency during operation, if needed. An internally connected pulldown

resistor of about 400 k

Ω on this pin acts the same way as one on the DEF pin (see Pin-Selectable Output

Voltage (DEF)).

8.3.6 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents faulty operation of the device by switching off both

the power FETs. The typical undervoltage-lockout threshold setting is 2.7 V. The device is fully operational for

voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts

operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV.

8.3.7 Thermal Shutdown

the device goes into thermal shutdown. Both the high-side and low-side power FETs turn off and PG goes into

operation, beginning with soft start. To avoid unstable conditions, the device implements a hysteresis of typically

20°C on the thermal shutdown temperature.

8.4 Device Functional Modes

8.4.1 Pulse-Width Modulation (PWM) Operation

The TPS6215x operates using pulse-width modulation in continuous-conduction mode (CCM) with a nominal

switching frequency of 2.5 MHz or 1.25 MHz, selectable with the FSW pin. The frequency variation in the PWM

the output current is higher than half the inductor ripple current. To maintain high efficiency at light loads, the

device enters power-save mode at the boundary of discontinuous conduction mode (DCM). This happens if the

output current becomes smaller than half the inductor ripple current.

(1)

Maximum allowed voltage is 7 V. Therefore,the recommended connection for DEF is to VOUT, not VIN.

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