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MT48LC8M16A2FC-7EL Datasheet(PDF) 48 Page - Micron Technology |
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MT48LC8M16A2FC-7EL Datasheet(HTML) 48 Page - Micron Technology |
48 / 59 page 48 128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc. 128Mb: x4, x8, x16 SDRAM READ – DQM OPERATION 1 tCH tCL tCK tRCD CAS Latency DQM / DQML, DQMH CKE CLK A0-A9, A11 DQ BA0, BA1 A10 tCMS ROW BANK ROW BANK tAC LZ DOUT m tOH DOUT m + 3 DOUT m + 2 t tHZ LZ t tCMH COMMAND NOP NOP NOP ACTIVE NOP READ NOP NOP NOP tHZ tAC tOH tAC tOH tAH tAS tCMS tCMH tAH tAS tAH tAS tCKH tCKS ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE COLUMN m 2 T0 T1 T2 T4 T3 T5 T6 T7 T8 DON’T CARE UNDEFINED NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. x16: A9 and A11 = “Don’t Care” x8: A11 = “Don’t Care” *CAS latency indicated in parentheses. -7E -75 -8E SYMBOL* MIN MAX MIN MAX MIN MAX UNITS tCKS 1.5 1.5 2 ns tCMH 0.8 0.8 1 ns tCMS 1.5 1.5 2 ns tHZ(3) 5.4 5.4 6 ns tHZ(2) 5.4 6 6 ns tLZ 111 ns tOH 333 ns tRCD 15 20 20 ns TIMING PARAMETERS -7E -75 -8E SYMBOL* MIN MAX MIN MAX MIN MAX UNITS tAC (3) 5.4 5.4 6 ns tAC (2) 5.4 6 6 ns tAH 0.8 0.8 1 ns tAS 1.5 1.5 2 ns tCH 2.5 2.5 3 ns tCL 2.5 2.5 3 ns tCK (3) 7 7.5 8 ns tCK (2) 7.5 10 10 ns tCKH 0.8 0.8 1 ns |
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