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MT48LC8M16A2FB-7EL Datasheet(PDF) 30 Page - Micron Technology

Part # MT48LC8M16A2FB-7EL
Description  SYNCHRONOUS DRAM
Download  59 Pages
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT48LC8M16A2FB-7EL Datasheet(HTML) 30 Page - Micron Technology

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128Mb: x4, x8, x16 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
©2001, Micron Technology, Inc.
128Mb: x4, x8, x16
SDRAM
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands
must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is
met, the SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been
met. Once tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is
met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.


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