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MT48LC8M16A2FC-7E Datasheet(PDF) 22 Page - Micron Technology |
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MT48LC8M16A2FC-7E Datasheet(HTML) 22 Page - Micron Technology |
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22 / 59 page  22 128Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 128MSDRAM_E.p65 – Rev. E; Pub. 1/02 ©2001, Micron Technology, Inc. 128Mb: x4, x8, x16 SDRAM WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are pro- vided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the ge- neric WRITE commands used in the following illustra- tions, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any addi- tional input data will be ignored (see Figure 14). A full- page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE com- mand, and the data provided coincident with the new Figure 15 WRITE to WRITE command applies to the new command. An example is shown in Figure 15. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch archi- tecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 16, or each subsequent WRITE may be performed to a different bank. CLK DQ DIN n T2 T1 T3 T0 COMMAND ADDRESS NOP NOP WRITE DIN n + 1 NOP BANK, COL n NOTE: Burst length = 2. DQM is LOW. Figure 14 WRITE Burst DON’T CARE CLK DQ T2 T1 T0 COMMAND ADDRESS NOP WRITE WRITE BANK, COL n BANK, COL b DIN n DIN n + 1 DIN b NOTE: DQM is LOW. Each WRITE command may be to any bank. Figure 13 WRITE Command CS# WE# CAS# RAS# CKE CLK COLUMN ADDRESS A10 HIGH ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE A0-A9, A11: x4 A0-A9: x8 A0-A8: x16 A11: x8 A9, A11: x16 BA0,1 BANK ADDRESS |
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